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quad, 1 6 - bit, 2.4 gsps, txdac+? digital - to - anal og conv erter data sheet AD9154 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent r ights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com features supports input data rate s up to 1 gsps proprietary , low spurious and distortion design sin gle carrier lt e 20 mh z bandwidth ( bw ) , aclr = 7 7 dbc at 18 0 mhz if six carrier gsm imd = 78 dbc, 600 khz ca rrier spacing at 180 mh z if s fdr = 72 dbc a t 180 mhz if , ? 6 dbfs single tone flexible 8 - lane jesd 204 b interface multiple chip synchronization fixed latency data generator latency compensation input signal power detection high performance, low noise phase - locked loop ( pll ) clock multiplier digital i nverse sinc fi lter digital quadrature modulation using a numerically controlled oscillator ( nco ) nyquist band selection m ix mode selectable 1 , 2 , 4, and 8 i nterpolation filters low po we r : 2 .1 1 w at 1. 6 gsps, full oper ating conditions 88 - lead, exposed pad lfcsp app lications wireless communications multicarrier lte and gsm b ase s tations wideband repeaters software defined radios wideband communications point to point microwave radi o transmit diversity , multiple input/multiple output ( mimo ) instrumentation automated test equipment functional block dia gram figure 1. general description the AD9154 is a quad, 16 - bit, high dynamic range digital - to - analog converter (dac) that provide s a maximum sample rate of 2.4 gsps, permitting multicarrier generation up to the nyquist frequency in baseband mode. the AD9154 includes features optimized for direct conversion transmit applicat ions, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. the dac outputs are optimized to interface seamlessly with the adrf6720 - 27 radio frequency quadrature modulator (aqm ) from analog devices, inc. in mix mode, the AD9154 dac can reconstruct ca rriers in the second and third nyquist z ones. a serial port interface (spi) provi des the programm ing/readback of internal parameters. the f ull - scale output current can be programmed over a range of 4 ma to 2 0 ma. the AD9154 is available in two different 88- lead lfcsp packages . product highlights 1. u ltrawide signal bandwidth enables emerging wideband and multiband wireless applications. 2. advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequ encies. 3. jesd 204 b subclass 1 support simplifies multichip synchronization. 4. small package size with a 12 mm 12 mm footprint. quad mod adrf6720-27 quad dac jesd204b 0/90 phase shifter dac dac lo_in mod_spi dac clock dac spi AD9154 quad mod adrf6720-27 lpf lpf 0/90 phase shifter jesd204b syncoutx syncoutx lo_in mod_spi dac dac sysref rf output 1 rf output 1 1389-101
AD9154 data sheet rev. b | page 2 of 124 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 3 detailed functional block diagram .............................................. 4 specifications ..................................................................................... 5 dc specifications ......................................................................... 5 digital specifications ................................................................... 6 maximum dac update rate speed specifications by supply .... 7 jesd204b serial interface speed specifications ...................... 7 sys ref to dac clock timing specifications ......................... 8 digital input data timing specifications ................................. 8 latency variation specifications ................................................ 9 jesd204b interface electrical specifications ........................... 9 ac specifications ........................................................................ 10 absolute m aximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configur ation and function descriptions ........................... 12 typical performance characteristics ........................................... 14 terminology .................................................................................... 20 theory of operation ...................................................................... 21 serial port operation ..................................................................... 22 data format ................................................................................ 22 serial port pin descriptions ...................................................... 22 serial port options ..................................................................... 22 chip information ............................................................................ 24 device setup guide ........................................................................ 25 step 1: start up the dac ........................................................... 25 step 2: digital datapath ............................................................. 26 step 3: transport layer .............................................................. 26 step 4: physical layer ................................................................. 27 step 5: data link layer .............................................................. 28 step 6: error monitoring ........................................................... 28 dac pll setup ............................................................................ 28 interpolation ............................................................................... 29 jesd204b setup .......................................................................... 29 equalization mode setup .......................................................... 30 link latency setup ..................................................................... 30 crossbar setup ............................................................................ 32 jesd204b serial data interface .................................................... 33 jesd204b overview .................................................................. 33 physical layer ............................................................................. 34 data link layer .......................................................................... 37 transport layer .......................................................................... 4 5 jesd204b test modes ............................................................... 58 jesd204b error monitoring ..................................................... 59 digital datapath ............................................................................. 62 dual paging ................................................................................. 62 data format ................................................................................ 62 interpolation modes .................................................................. 62 digital modulation ..................................................................... 63 inverse sinc ................................................................................. 64 digital gain, phase adjust, dc offset, and group delay .... 64 i to q swap .................................................................................. 65 nco alignment ......................................................................... 65 downstream protection ............................................................ 66 datapath prbs ........................................................................... 68 d c te st mo d e ............................................................................. 69 interrupt request operation ........................................................ 70 interrupt service routine .......................................................... 70 dac input clock configurations ................................................ 72 driving the clk inp uts .......................................................... 72 dac pll fixed register writes ............................................... 72 condition specific register writes .......................................... 72 starting the pll .......................................................................... 73 analog outputs ............................................................................... 75 transmit dac operation .......................................................... 75 normal and mix modes of operation ..................................... 76 temperature sensor ....................................................................... 77 example start - up sequence .......................................................... 78 step 1: start up the dac ........................................................... 78 step 2: digital datapath ............................................................. 78 step 3: transport layer .............................................................. 79 step 4: physical layer ................................................................. 79 step 5: data link layer .............................................................. 80 step 6: error monitoring ........................................................... 80 board level hardware considerations ........................................ 81
data sheet AD9154 rev. b | page 3 of 124 power supply recommendations ............................................. 81 jesd204b serial interface inputs (serdin0 to serdin7) . 81 register summary ........................................................................... 84 register details ................................................................................ 91 outline dimensions ...................................................................... 123 ordering guide ............................................................................. 124 revision history 7 /15 rev . a to rev. b changes to general description section ....................................... 1 chang e s to figure 33 ...................................................................... 19 added figure 34 ; renumbered sequentially ............................... 19 changes to figure 43 ...................................................................... 35 changes to serdes pll fixed register writes section ........... 36 change to table 87 .......................................................................... 79 change to errwindow , table 93 ............................................ 95 updated outline dimensions ......................................................123 changes to ordering guide .........................................................123 3 / 15 rev . 0 to rev. a changes to figure 1 and general description section ................ 1 2 / 15 rev ision 0 : initial version
AD9154 data sheet rev. b | page 4 of 124 detailed functional block diagram figure 2. detailed functional block diagram 11389-001 sdio sclk cs irq reset syncout0? syncout0+ pdp out1 pdp out0 dac pll serdes pll power-on reset serial i/o port config registers clk_sel dacclk pll_lock synchronization logic dac align detect hb1 txen0 txen1 serdin7 serdin0 v tt clock data recovery and clock formatter syncout1+ syncout1? ref and bias i120 sysref+ sysref? sdo hb3 hb2 dacclk out3+ out3? inv sinc f dac 4, 8 nco complex modulation phase adjust q gain i gain sysref rcvr clk+ clk? mode control dacclk clk rcvr hb3 hb2 hb1 q offset i offset hb1 hb3 hb2 mode control hb3 hb2 hb1 fsc fsc out2+ out2? dacclk out1+ out1? inv sinc f dac 4, 8 nco complex modulation phase adjust q gain i gain q offset i offset fsc fsc out0+ out0? clock distribution and control logic pdp1 pdp0
data sheet AD9154 rev. b | page 5 of 124 specifications dc specifi cations avdd33 = 3.3 v, siovdd33 = 3.3 v, iovd d = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40 c to + 85 c, i outfs = 20 ma, unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit resolution 16 bits accuracy differential nonlinearity (dnl) 4.3 lsb integral nonlinearity (inl) 8.2 lsb main dac outputs gain error with internal reference ? 8.0 ? 3.01 + 8.0 % fsr offse t error 1 2322 ppm i/q gain mismatch ?3.0 +0.54 +3.0 % fsr full - scale output current based on a 4 k external resistor between i 120 and ground max imum setting 19.9 20.85 21.3 ma minimum setting 3.9 4.17 4.4 ma output compliance range 2.0 2.8 3.37 v output resistance 15 m output capacitance 3.0 pf full - scale current dac monotonicity guaranteed main dac temperature drift gai n 2 ? 114 ppm/c reference internal reference voltage 1.2 v analog supply voltages avdd 33 5% 3.13 3.3 3.47 v pvdd 12 5% 1.14 1.2 1.26 v 2% 1.274 1.3 1.326 v cvdd 12 5% 1.14 1.2 1.26 v 2% 1.274 1.3 1.326 v digital supply voltages siovdd 33 5% 3.13 3.3 3.47 v v tt 1.1 1.2 1.37 v dvdd 12 5% 1.14 1.2 1.26 v 2% 1.274 1.3 1.326 v svdd 12 5% 1.14 1.2 1.26 v 2% 1.274 1.3 1.326 v iovdd 5% 1.71 1.8 3.47 v power consumption 2 interpolation mode, jesd 204b mode 4, dual link, 8 serdes lanes f dac = 1. 6 gsps, nco on , if out = 40 mhz, pll on , dac full - scale current = 20 ma 2.11 2.63 w avdd 33 159 185 ma pvdd 12 152 174 ma cvdd 12 355 397 ma svdd 12 includes v tt 541.9 682 ma dvdd 12 264.5 442 ma siovdd 33 + iovdd 10.6 11.4 ma 1 offset error is a measure of how far from full - scale range (fsr) the dac output current is at 25 c (in ppm) . 2 gain drift is a measure of the slope of the dac output current across its full temp erature range (in ppm/ c) .
AD9154 data sheet rev. b | page 6 of 124 digital specificatio ns a vdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40 c to + 85 c, i outfs = 20 ma, unless otherwise noted. table 2 . parameter symbol test conditions/comments min typ max unit cmos input logic level input voltage (v in ) logic high 1.8 v iovdd 3.3 v 0.7 iovdd v low 1.8 v iovdd 3.3 v 0.3 iovdd v cmos output logic level output voltage (v out ) logic high 1.8 v iovdd 3.3 v 0.3 iovdd v maximum dac update rate 1 1 interpolation 2 (see table 4 ) 1096 msps 2 interpolation 3 2192 msps 4 interpolation 2400 msps 8 interpolation 2400 msps adjusted dac update rate 1 interpolation 1096 msps 2 interpolation 1096 msps 4 interpolation 600 ms ps 8 interpolation 300 msps interface 4 number of jesd 204 b lanes 8 lanes jesd 204 b serial interface speed minimum per lane 1. 4 4 gbps maximum per lane, svdd12 = 1.3 v 2% 10.96 gbps dac clock input (clk ) differentia l peak - to - peak voltage 400 1000 2000 mv common - mode voltage self biased input, ac - coupled 600 mv maximum clock rate , dac clock sourced directly from cl k 2 4 00 mhz pll multiplier mode clock input frequency 5 6 .0 ghz f vco 12. 0 ghz 35 1000 mhz sysref input (sysref ) differential peak - to - peak voltage 400 1000 2000 mv common - mode voltage 0 2000 mv sysref frequency 6 f data /(k (f/s)) hz sysref t o dac clock 7 sysref differential swing = 0 .4 v, slew rate = 1.3 v/ns, ( ac - coupled, and 0 v, 0.6 v, 1.25 v, 2.0 v dc - coupled common - mode voltages) setup time t ssd 111 p s hold time t hsd 145 ps spi see timing diagrams shown in figure 39 and figure 40 maximum clock rate sclk iovdd = 1.8 v 10 mhz minimum sclk pulse width high t pwh 8 ns low t pwl 12 ns sdio to sclk setup time t ds 5 ns hold time t dh 2 ns sdo to sclk data valid window t dv 25 ns
data sheet AD9154 rev. b | page 7 of 124 parameter symbol test conditions/comments min typ max unit cs to sclk setup time t s cs 5 ns hold time t hcs cs 2 ns 1 see table 3 for detailed specificatio ns for dac update rate conditions. 2 maximum speed for 1 interpolation is limited by the jesd204b interface. see table 4 for details. 3 maximum speed for 2 interpolation is limited by the jesd204b interface. see table 4 for details. 4 see table 4 for detailed specificat ions for jesd204b speed conditions. 5 clk+/clk? serve as a reference oscillator input for the on-chip pll clock multiplier when in use. 6 k, f, and s are jesd204b transport layer parame ters. see table 42 for the full definitions. 7 see table 5 for detailed specifications for sysref to dac clock timing conditions. maximum dac update rate speed specifications by supply avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40c to +85c, i outfs = 20 ma, unless otherwise noted. table 3. parameter test conditions/comments min typ max unit maximum dac update rate dvdd12, cvdd12, pvdd12 = 1.2 v 5% 1.93 gsps dvdd12, cvdd12, pvdd12 = 1.2 v 2% 2.07 gsps dvdd12, cvdd12, pvdd12 = 1.3 v 2% 2.4 gsps jesd204b serial interfac e speed specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40c to +85c, i outfs = 20 ma, unless otherwise noted. table 4. parameter test conditions/comments min typ max unit clock and data recovery (cdr) half rate mode svdd12 = 1.2 v 5% 5.74 9.04 gbps svdd12 = 1.2 v 2% 5.74 9.65 gbps svdd12 = 1.3 v 2% 5.74 10.96 gbps cdr full rate mode svdd12 = 1.2 v 5% 2.87 4.79 gbps svdd12 = 1.2 v 2% 2.87 4.93 gbps svdd12 = 1.3 v 2% 2.87 5.73 gbps cdr oversampling mode svdd12 = 1.2 v 5% 1.44 2.39 gbps svdd12 = 1.2 v 2% 1.44 2.50 gbps svdd12 = 1.3 v 2% 1.44 2.93 gbps
AD9154 data sheet rev. b | page 8 of 124 sysref to dac clock timing specification s avdd33 = 3.3 v, siovdd33 = 3. 3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40 c to + 85 c, i outfs = 20 m a, sysref common - mode voltages = 0.0 v, 0.6 v, 1.25 v, and 2.0 v, unless otherwise noted. table 5 . parameter test conditions/comments min typ max unit sysref d ifferential swing = 0.4 v, slew rate = 1.3 v/ns setup time ac -c oupled 89 ps dc - coupled 111 ps hold time ac - coupled 105 ps dc - coupled 145 ps differential swing = 0.7 v, slew rate = 2.28 v/ns setup time ac - coupled 71 ps dc - coupled 81 ps hold time ac - coupled 97 ps dc - coupled 118 ps dif ferential swing = 1.0 v, slew rate = 3.26 v/ns setup time ac - coupled 58 ps dc - coupled 64 ps hold time ac - coupled 92 ps dc - coupled 108 ps digital input data t iming specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = 25c, i outfs = 20 ma, unless otherwise noted. table 6 . parameter test conditions/comments min typ max unit latency interface , excluding transport l ayer d elay buffer 17 pclock 1 cycles interpolation with or without modulation 1 94 dac clock cycles 2 130 dac clock cycles 4 250 dac clock cycles 8 474 dac clock cycles inverse sinc 17 dac clock cycles fine modulation 20 dac clock cycles coarse modulation f s / 8 8 dac clock cycles f s /4 4 dac clock cycles digital phase adjust 12 dac clock cycles digital gain adjust 12 dac clock cycles power - up time dual a only register 0 x 011 from 0 x 60 to 0 x 00 30 s dual b only register 0 x 011 from 0 x 18 to 0 x 00 30 s all dacs register 0x011 from 0x7 8 to 0 x 00 30 s 1 pclock is the AD9154 int ernal processing clock running at the jesd204b lane rate 40.
data sheet AD9154 rev. b | page 9 of 124 latency variation sp ecifications avdd33 = 3.3 v, siov dd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = 25c, i outfs = 20 ma, unle ss otherwise noted. table 7 . parameter test conditions/comments min typ max unit dac latency variation subclass 1 pll off 0 1 dacclk cycles pll on ? 1 + 1 dacclk cycles jesd204b interface e lectrical specificat ions avdd33 = 3.3 v, siovdd 33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = ?40 c to + 85 c, i outfs = 20 ma, unless otherwise noted. table 8 . parameter symbol test conditions/comments min typ max unit jesd 204 b data inputs input leakage current t a = 25c logic high input level = 1.2 v 0.25 v, v tt = 1.2 v 10 a logic low input level = 0 v ? 4 a unit interval ui 94 714 ps common - mode voltage v rcm ac - coupled ? 0.05 + 1.85 v v tt = svdd12 1 differential voltage r_v diff 110 1050 mv v tt source impedance z tt at dc 30 differential impedance z rdiff at dc 80 100 120 differential return loss rl rdif 8 db common - mode return loss rl rcm 6 db differential outputs ( syncout ) 2 output offset voltage v os 1.19 1.27 v deterministic latency fixed 17 pclock 3 cycles variable 2 pclock 3 cycles s ysr ef to local multiframe clock ( lmfc ) delay 4 dac clock cycles 1 as measured o n the input side of the ac coupling capacitor. 2 ieee standard 1596.3 lvds compatible. 3 pclock is the AD9154 interna l processing clock; its frequency is equal to the jesd204b lane rate 40.
AD9154 data sheet rev. b | page 10 of 124 ac specifications avdd33 = 3.3 v, siovdd33 = 3.3 v, iovdd = 1.8 v, dvdd12 = 1.2 v, cvdd12 = 1.2 v, pvdd12 = 1.2 v, svdd12 = 1.2 v, v tt = 1.2 v, t a = 25 c, i outfs = 20 ma, unless othe rwise noted. table 9 . parameter test conditions/comments min typ max unit spurious - free dynamic range (sfdr) ? 6 dbfs single tone f dac = 1966.08 msps f out = 20 mhz 76 dbc f dac = 1966.08 msps f out = 150 mhz 7 3 dbc f dac = 1966.08 msps f out = 1 8 0 mhz 72 dbc two - tone third intermodulation distortion (imd) ? 6 dbfs f dac = 983.04 msps f out = 3 0 mhz 87 dbc f dac = 983.04 msps f out = 150 mhz 77 dbc f dac = 1966.08 msps f out = 3 0 mhz 86 dbc f dac = 1966.08 msps f out = 1 8 0 mhz 78 dbc noise spectral density (nsd), single tone 0 dbfs f dac = 983.04 msps f out = 150 mhz ? 16 4 dbm/hz f dac = 1966.08 msps f out = 1 8 0 mhz ? 163 dbm/hz 5 mh z bw lte first adjacent channel leakage ratio (aclr), single carrier 0 dbfs , p ll off f dac = 1966.08 msps f out = 5 0 mhz 7 9 dbc f dac = 1966. 08 msps f out = 150 mhz 77 dbc f dac = 1966.08 msps f out = 1 8 0 mhz 7 7 dbc 5 mh z bw lte second aclr, single carrier 0 dbfs , pll off f dac = 1966.08 msps f out = 5 0 mhz 82 dbc f da c = 1966.08 msps f out = 150 mhz 81 dbc f dac = 1966.08 msps f out = 18 0 mhz 81 dbc
data sheet AD9154 rev. b | page 11 of 124 absolute maximum rat ings table 10. parameter rating i 120 to ground ? 0.3 v to avdd 33 + 0.3 v serdinx, v tt , syncoutx , and txenx ?0.3 v to s io vdd 33 + 0.3 v outx ? 0.3 v to avdd 33 + 0.3 v sysref gnd ? 0.5 v clk to ground ? 0.3 v to pvdd 12 + 0.3 v reset , irq , cs , sclk, sdio, sdo, and p dp outx to ground ? 0.3 v to iovdd + 0.3 v ldo_byp 1 ? 0.3 v to svdd 12 + 0.3 v ldo_byp 2 ? 0.3 v to pvdd 12 + 0.3 v ambient operating temperature (t a ) ? 40 c to + 85 c junction temperature 125 c storage temperature ?65c to + 150 c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operati onal section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance the exposed pad (epad) must be soldered to the ground plane for the 88 - lea d lfcsp. the epad provides an electrical, thermal, and mechanical connection to the board. typical ja , jb , and jc values are specified for a 4 - layer , jesd 51- 7 high effective thermal conductivity test board for leaded surface - mount packages. ja is obtained in still air conditions (jesd51 - 2). airflow increases heat dissipation, effectively red ucing ja . jb is o btained following double - ring cold plate test conditions (jesd51 - 8). jc is obtained with the test case temperature moni - tored at the bottom of the exposed pad. jt and jb are thermal characteristic parameters obtained with ja in still air test conditions. junction temperature (t j ) can be estimated using the following equations: t j = t t + ( jt p ), or t j = t b + ( jb p ) where: t t is the temperature measured at the top of the package. p is the total device power dissipation. t b is the temperature measured at the board. table 11 . thermal resistance package ja jb jc jt jb unit 88 - lead lfcsp 1 22.6 5.59 1.17 0.1 5.22 c/w 1 the exposed pad must be securely connected to the ground plane. esd caution
AD9154 data sheet rev. b | page 12 of 124 pin configuration an d function descripti ons figure 3. pin configuration table 12 . pin function descriptions pin no. mnemonic description 1, 4, 7 , 8, 9, 10, 56, 57 pvdd 12 1.2 v clock supplies. 2 cl k+ pll reference/clock input, positive. when the pll is used, this pin is the positive reference clock input. when the pll is not used, this pin is the positive device clock input. this pin is self biased and must be ac - coupled. 3 clk? pll reference/clock input, negative. when the pll is used, this pin is the negative reference clock input. when the pll is not used, this pin is the negative devic e clock input. this pin is self biased and must be ac - coupled. 5 sysref+ timing referen ce input , positive. this pin is u sed in jesd204b subclass 1 s ystems and is s elf biased , ac - coupled , or dc - coupled . 6 sysref? timing reference input , negative. this pin is us ed in jesd204b subclass 1 systems and is self biased, ac - coupled, or dc - coupled. 11 txen 0 t ransmit ena ble for dac0 and dac1. cmos levels are determined with respect to iovdd . 12 txen 1 t ransmit enable for dac2 and dac3. cmos levels are determined with respect to iovdd. 13 , 14 , 53 dvdd 12 1.2 v digital supplies . 15 serdin 0 + serial channel input 0, positive. cml compliant. serdin0+ is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 16 serdin 0 ? serial channel input 0, negative. cml compliant. serdin0? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only . 17, 20 , 22, 28, 31, 32, 33, 36, 39, 45, 47 , 50 svdd 12 1.2 v jesd204b receiver supplies . 18 serdin 1 + serial channel input 1, positive. cml compliant. serdin1 + is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 19 serdin 1 ? serial channel input 1, negat ive. cml compliant. serdin1 ? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 21 , 25, 42, 46 v tt 1 .2 v termination voltage pins . 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 pvdd12 clk+ clk? pvdd12 sysref+ sysref? pvdd12 pvdd12 pvdd12 notes 1. the exposed p ad must be secure l y connected t o the ground plane. 2. dnc = do not connec t . pvdd12 txen0 txen1 dvdd12 dvdd12 serdin0+ serdin0? 17 svdd12 18 serdin1+ 19 serdin1? 20 svdd12 23 24 25 26 27 28 29 30 31 32 33 34 36 37 syncout0+ syncout0? v tt serdin2+ serdin2? svdd12 serdin3+ serdin3? svdd12 svdd12 svdd12 ldo_byp1 35 siovdd33 svdd12 serdin4? 38 serdin4+ 39 svdd12 40 serdin5? 41 serdin5+ 58 57 56 55 54 53 52 51 50 49 48 47 46 45 pdp out1 59 pdp out0 60 irq 61 reset 62 sdo 63 sdio 64 sclk 65 cs 66 iovdd pvdd12 pvdd12 dnc dnc dvdd12 serdin7+ serdin7? svdd12 serdin6+ serdin6? svdd12 v tt svdd12 78 77 76 75 74 73 72 71 70 69 68 67 out1+ out1? 79 80 a vdd33 81 cvdd12 82 a vdd33 83 out0? 84 out+ 85 a vdd33 86 i120 87 cvdd12 88 ldo_byp2 a vdd33 cvdd12 a vdd33 out2+ out2? a vdd33 cvdd12 a vdd33 out3? out3+ a vdd33 1 1389-002 21 v tt 22 svdd12 42 v tt 43 syncout1? 44 syncout1+ AD9154 t op view (not to scale)
data sheet AD9154 rev. b | page 13 of 124 pin no. mnemonic description 23 syncout0+ positive lvds sync hronization output signal for channel link 0 . 24 syncout0? negative lvds synchronization output signal for channel link 0 . 26 serdin 2 + serial channel input 2, positive. cml compliant. serdin 2 + is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 27 serdin 2 ? serial channel input 2, negative. cml compliant. serdin2 ? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 29 serdin 3 + serial channel input 3 , positive. cml compliant. serdin3 + is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 30 serdin 3 ? serial channel input 3, negat ive. cml compliant. serdin3 ? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 34 ldo_byp 1 ldo serde s bypass. this pin requires a 1 resistor in series with a 1 f capacitor to ground. 35 siovdd 33 serdes ports i nput /o utput supply . 37 serdin 4 ? serial channel input 4, negative. cml compliant. serdin4 ? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 38 serdin 4 + serial channe l input 4 , positiv e. cml compliant. serdin4 + is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 40 serdin 5 ? serial channel input 5 , negative. cml compliant. serdin5 ? is internally terminated to t he v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 41 serdin 5 + serial channel input 5 , positive. cml compliant. serdin5 + is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - couple d only. 43 syncout1? negative lvds synchronization output signal for channel link 1 . 44 syncout1+ positive lvds synchronization output signal for channel link 1 . 48 serdin 6 ? serial channel input 6, negative. cml compl iant. serdin6 ? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 49 serdin 6 + serial channel input 6, positive. cml compliant. serdin6 + is internally terminated to the v tt pin voltage using a cal ibrated 50 resistor. this pin is ac - coupled only. 51 serdin 7 ? serial channel input 7, negative. cml compliant. serdin7 ? is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 52 serdin 7 + serial ch annel input 7 , positive. cml compliant. serdin7 + is internally terminated to the v tt pin voltage using a calibrated 50 resistor. this pin is ac - coupled only. 54 , 55 d nc do not connect. do not connect to this pin. 58 pdp out 1 power detection and protect ion (pdp) indicator for dac2 and dac3. 59 pdp out 0 pdp indicator for dac 0 and dac 1 . 60 irq interrupt request (active low, open drain). 61 reset reset (active low). cmos levels with are determined with respect to iovdd . 62 sdo serial port data output . cmos levels with are determined with respect to iovdd. 63 sdio serial port data input/output . cmos levels with are determined with respect to iovdd. 64 sclk serial port clock input . cmos levels with are determined with respect to iovdd. 65 cs serial port chip select (active low). cmos levels with are determined with respect to iovdd. 66 iovdd cmos i nput /o utput and spi pin supply . 67, 70, 72, 75, 77 , 80, 82 , 85 avdd 33 3.3 v analog supplies for the da c cores. 68 out 3 + dac 3 positive current output. 69 out 3 ? dac 3 negative current output. 71 , 76 , 81, 87 cvdd 12 1.2 v clock suppl ies. 73 out 2 ? dac 2 negative current output. 74 out 2 + dac 2 positive current output. 78 out 1 + dac 1 positive current output. 79 out 1 ? dac 1 negative current output. 83 out 0 ? dac0 negative current output. 84 out 0 + dac 0 positive current output. 86 i 120 output current generation pin for dac full - scale current. tie a 4 k resistor from this pin to ground . 88 ldo_byp 2 ldo clock bypass for the dac pll. tie a 1 resistor in series wit h a 1 f capacitor from this pin to ground. epad exposed pad. the exposed pad must be securely connected to the g rou nd plane.
AD9154 data sheet rev. b | page 14 of 124 typical performance characteristics figure 4 . single tone (0 dbfs) sfdr vs. f out in the first nyqu ist zone over f dac = 1966.08 mh z and 1228.80 mh z, all four dac outputs figure 5 . single tone (0 dbfs) sfdr vs. f out in the first nyquist zone over f dac = 1474.56 mh z and 983.04 mhz, all fou r dac outputs figure 6 . single tone (0 dbfs) sfdr vs. f out in the first nyquist zone over f dac = 1966.08 mh z, 1474.56 mhz, 1228.8 mh z , and 983.04 mh z figure 7. single tone sfdr vs. f out in the first nyquist zone over digital back off , f dac = 1966.08 mhz figure 8. in - band second harmonic vs. f out in the first nyquist zone over digital back off, f dac = 1966.08 mhz figure 9. in - band third harmonic vs. f out in the first nyquist zon e, f dac = 1966.08 mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 sfdr (dbc) f out (mhz) 1 1389-104 f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 sfdr (dbc) 1 1389-105 f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 sfdr (dbc) 1 1389-106 f dac = 9 8 3.04 m h z f dac = 1 2 28.8 m h z f dac = 1 4 74.5 6 mh z f dac = 1 9 66.0 8 mh z f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 sfdr (dbc) 1 1389-107 0dbfs ?6dbfs ?12dbfs ?15dbfs f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 in-band second harmonic (dbc) 1 1389-108 0dbfs ?6dbfs ?12dbfs ?15dbfs f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 in-band third harmonic (dbc) 1 1389-109 0dbfs ?6dbfs ?12dbfs ?15dbfs
data sheet AD9154 rev. b | page 15 of 124 figure 10 . in - band second harmonic vs. f out in the firs t nyquist zone over analog full - scale current, f dac = 1966.08 mhz fi gure 11 . in - band third har monic vs. f out in the fir s t nyquist zone over analog full - scale current, f dac = 1966.08 mhz figure 12 . two - tone third harmonic (imd3) vs. f out , f dac = 1966.08 mhz, 1474.56 mh z, 1228.8 mh z , and 983.04 mh z figure 13 . two - tone third harmonic ( imd 3) vs. f out over digital backoff figure 14 . two - tone third harmonic ( imd 3) vs. f out over analog full - scale current, f dac = 1966.08 mhz figure 15 . single tone (0 dbfs) nsd vs. f ou t over f dac = 1966.08 mhz, 1474.56 mh z, 1228.8 mh z, and 983.04 mh z at 70 mh z f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 in-band second harmonic (dbc) 1 1389- 1 10 20m a 10m a 4m a f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 in-band third harmonic (dbc) 1 1389- 11 1 20m a 10m a 4m a f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 imd3 (dbc) 1 1389- 1 12 f dac = 9 8 3.04 m h z f dac = 1 2 28.8 m h z f dac = 1 4 74.5 6 mh z f dac = 1 9 66.0 8 mh z f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 imd3 (dbc) 1 1389- 1 13 0dbfs ?6dbfs ?12dbfs ?15dbfs f out (mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 100 200 300 400 500 600 700 800 900 1000 imd3 (dbc) 1 1389- 1 14 20m a 10m a 4m a ?170 ?165 ?160 ?155 ?150 ?145 ?140 ?135 ?130 f out (mhz) 0 100 200 300 400 500 600 700 800 900 1000 1 1389- 1 15 nsd (dbm/hz) f dac = 9 8 3.04 m h z f dac = 1 2 28.8 m h z f dac = 1 4 74.5 6 mh z f dac = 1 9 66.0 8 mh z
AD9154 data sheet rev. b | page 16 of 124 figure 16 . single tone (0 dbfs) nsd vs. f out over f dac , 20 mh z offset from carrier figure 17 . single tone nsd vs. f out o ver digital back off, f dac = 1966.08 mhz , measured at 70 mh z figure 18 . single tone nsd vs. f out , f dac = 1966.08 mhz, measured at 70 m h z, pll on and off figure 19 . 1- ch annel ( 1c ) 5 mh z bw lte, first adjacent aclr vs. f out , pll on and off figure 20 . 1c 5 mh z bw lte, second adjacent aclr vs. f out , p ll on and off figure 21 . two - tone, third imd performance, if = 180 mh z, f dac = 1966.08 mhz ?170 ?165 ?160 ?155 ?150 ?145 ?140 ?135 ?130 f out (mhz) 1 1389- 1 16 nsd (dbm/hz) 100 0 200 300 400 500 f dac = 9 8 3.04 m h z f dac = 1 2 28.8 m h z f dac = 1 4 74.5 6 m h z f dac = 1 9 66.0 8 m h z ?170 ?165 ?160 ?155 ?150 ?145 ?140 ?135 ?130 f out (mhz) 0 100 200 300 400 500 600 700 800 900 1000 1 1389- 1 17 nsd (dbm/hz) 0dbfs ?6dbfs ?12dbfs ?15dbfs ?170 ?165 ?160 ?155 ?150 ?145 ?140 ?135 ?130 f out (mhz) 0 100 200 300 400 500 600 700 800 900 1000 1 1389- 1 18 nsd (dbm/hz) pll of f pll on f out (mhz) 0 100 200 300 400 500 600 700 800 900 1000 1 1389- 1 19 pll o f f pll on ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 first adjacent aclr (dbc) f out (mhz) 0 100 200 300 400 500 600 700 800 900 1000 1 1389-120 pll o f f pll on ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 second adjacent aclr (dbc) 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 center 180.550mhz #res bw 3.0khz span 10.00mhz sweep 22.80ms (1001pts) vbw 3.0khz (10db/div) 11389-121
data sheet AD9154 rev. b | page 17 of 124 fi gure 22 . 1c 5 mh z bw lte aclr performance, if = 180 mh z, f dac = 1966.08 mhz figure 23 . 1c 20 mh z bw l te aclr performance, if = 180 mh z, f dac = 1966.08 mhz figure 24 . singl e tone f dac = 1966.08 mhz, f out = 280 mhz, ?14 dbfs figure 25 . 2- channel ( 2c ) 5 mh z bw with 5 mh z gap , l te aclr performance, if = 180 mh z, f dac = 1966.08 mhz (total lte carrier power is 20.982 dbm) figure 26 . single tone sfdr f dac = 1966.08 mhz, 4 interpolation, f out = 10 mhz, ?14 dbfs figur e 27 . 6- channel ( 6c ) spaced by 600 kh z gsm , enhanced data rates for gsm evolution ( edge ) adjacent channel power ( acp ) imd perfor mance, if = 180 mh z, f dac = 1966.08 mhz ?25 ?125 ?115 ?105 ?95 ?85 ?75 ?65 ?55 ?45 ?35 center 180mhz #res bw 30khz span 44.5mhz sweep 144.3ms vbw 300khz (10db/div) 11389-122 ?81.6dbc ?81.3dbc ?81.3dbc ?78.8dbc ?12.9dbm ?78.5dbc ?81.1dbc ?81.7dbc ?82.1dbc ?35 ?135 ?125 ?115 ?105 ?95 ?85 ?75 ?65 ?55 ?45 center 180mhz #res bw 30khz span 140mhz sweep 454.1ms vbw 300khz (10db/div) 11389-123 ?77.3dbc ?77.4dbc ?76.2dbc ?13.1dbm ?75.8dbc ?77.2dbc ?77.2dbc ?10 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 start 0hz #res bw 30khz stop 2.0ghz sweep 54.20ms (1001pts) vbw 30khz (10db/div) 11389-124 ?35 ?135 ?125 ?115 ?105 ?95 ?85 ?75 ?65 ?55 ?45 center 175mhz #res bw 30khz span 54.5mhz sweep 2s vbw 300khz (10db/div) 11389-125 ?73.4dbc ?73.4dbc ?73.4dbc ?73.2dbc ?65.3dbc ?24.0dbm ?61.4dbc 0.0dbc ?61.4dbc ?73.5dbc ?73.3dbc ?100 ?110 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 start 0hz #res bw 30khz stop 2.000ghz sweep 54.20ms (1001pts) vbw 30khz (10db/div) 11389-126 ?35 ?25 ?125 ?115 ?105 ?95 ?85 ?75 ?65 ?55 ?45 center 180mhz #res bw 10khz span 10mhz #sweep 1s #vbw 100khz (10db/div) 11389-127 ?83.26dbc ?82.27dbc ?79.05dbc ?78.51dbc ?82.59dbc ?83.86dbc ?23.093dbm ?22.809dbm ?22.899dbm ?22.658dbm ?23.146dbm ?22.864dbm
AD9154 data sheet rev. b | page 18 of 124 figu re 28 . total power consumption vs. f dac over interpolation figure 29 . dvdd12 supply current vs. f dac over interpolation figure 30 . additive dvdd12 supply current vs. f dac over digital functions figure 31 . avdd33, cvdd12 , and pvdd12 supply current vs. f dac 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 0 500 1000 1500 2000 2500 t ot al power consumption (w) f dac (mhz) 1 interpol a tion 2 interpol a tion 4 interpol a tion 8 interpol a tion 1 1389-128 1 1389-129 0 50 100 150 200 250 300 350 400 450 500 dvdd12 supp l y current (ma) 1 interpol a tion 2 interpol a tion 4 interpol a tion 8 interpol a tion 0 500 1000 1500 2000 2500 f dac (mhz) 0 500 1000 1500 2000 2500 f dac (mhz) 1 1389-130 0 20 40 60 80 100 120 140 additive dvdd12 supp l y current (ma) nco f dac /4 f dac /8 inverse sinc digi t al gain, phase asdjus t , grou p del a y 1 1389-131 0 50 100 150 200 250 300 350 400 450 500 supp l y current (ma) a vdd33 cvdd12 pvdd12 0 500 1000 1500 2000 2500 f dac (mhz)
data sheet AD9154 rev. b | page 19 of 124 figure 32 . total ser des supply current ( svdd12) vs . lane rate: 2, 4 , and 8 lanes figure 33 . single tone phase noise vs. offset freque ncy at four different f out rates, f dac = 2.0 ghz, pll o ff figure 34 . single tone phase noise vs. offset freque ncy at four d ifferent f out rates, f dac = 2.0 ghz, pll on figure 35 . 1c 256 point quadrature amplitude modulation (qam) signal aclr performance, if = 180 mhz, f dac = 1966.08 mh z 0 100 200 300 400 500 600 700 800 1 2 3 4 5 6 7 8 9 t o t a l serdes supp l y current (ma) lane r a te (gbps) 1. 2 v , 8 l a n e s 1. 2 v , 4 l a n e s 1. 2 v , 2 l a n e s 1. 3 v , 8 l a n e s 1. 3 v , 4 l a n e s 1. 3 v , 2 l a n e s 1 1389-132 180 160 140 120 100 80 60 10 100 1k 10k 100k 1m 10m phase noise (dbc/hz) offset frequenc y (hz) 51mhz f alse 101mhz f alse 201mhz f alse 401mhz f alse 51mhz sma100 a 1 1389-233 180 160 140 120 100 80 60 10 100 1k 10k 100k 1m 10m phase noise (dbc/hz) offset frequenc y (hz) 51mhz true 101mhz true 201mhz true 401mhz true 51mhz sma100 a 1 1389-234 ?30 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 center 180mhz #res bw 30khz span 65.4mhz sweep 212.1ms #vbw 300khz (10db/div) 11389-135 ?81.3dbc ?81.1dbc ?80.8dbc ?80.3dbc ?77.8dbc ?77.3dbc ?80.7dbc ?81.5dbc ?81.9dbc ?82.0dbc ?13.3dbm
AD9154 data sheet rev. b | page 20 of 124 terminology integral nonlinearity (inl) inl is the maxim um deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated wit h a 1 lsb change in digital input code. offset error offset error is a measure of how far from full - scale range (fsr) the dac output current is at 25 c (in ppm). gain error gain error is the difference between the actual and ideal output span. the actual s pan is determined by the difference between the output when the input is at its minimum code and the output when the input is at its maximum code. output compliance range the output compliance range is the range of allowable voltages at the output of a cur rent output dac. operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient value (25c) to the value at either t min or t max . for offset and gai n drift, the drift is reported in ppm of fsr per degree celsius. settling time settling time is the time required for the output to reach and remain within a specified error band around its final valu e, measured from the start of the output transition. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to nyquist frequency of the dac. typically, energy in this band is rejected by the interpolation filters. this specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the dac output. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed that has a sharp transition band near f data /2. images that typically appear around f dac (output data rate) can be greatly suppressed. adjace nt channel leakage ratio (aclr) aclr is the ratio in decibels relative to the carrier (dbc) between the measured power within a channel relative to its adjacent channel. complex image rejection in a single sideba nd upconversion, two images are created aro und the second if frequency; the desired signal is o n one of these images . the other signal is unwanted, and a complex modulator rejects this unwanted image. adjusted dac update rate the adjusted dac update rate the dac update rate divided by the selected interpolati on factor. physical lane physical lane x refers to serdinx . logical lane logical lane x refers to physical lanes after optionally being remapped by the crossbar block (register 0 x 308 to register 0 x 30 b). link lane link lane x refers to logical lanes considered per link. whe n paging link 0 (register 0x300, bit 2 = 0), link lane x = logical lane x. whe n paging link 1 (register 0x300, bit 2 = 1 , dual link only), link lane x = logical lane x + 4 .
data sheet AD9154 rev. b | page 21 of 124 theory of operation th e AD9154 is a 16 - bit, quad dac with a serdes interface. figure 2 s hows a detailed functional block diagram of the AD9154 . eight high speed serial lan es carry data into the AD9154 . the clock for the input data is derived from the device clock (as called out in the jesd204b specification ) . this device clock can be s ourced with a phase - locked loop ( pll ) reference clock used by the on - chip pll to generate a dac clock or a high fidelity direct external dac sampling clock. the device can be configured to operate in one - , two - , four - , or eight - lane modes, depending on the required input data rate. t he quad dac can be configured as a dual link device with each jesd204b link providing data for a dual dac pair t o add application flexibility . the signal processing datapath of the AD9154 offers four interpolation modes (1, 2, 4, and 8) through three half - ba nd filters. an inverse sinc filter compensate s for dac output sinc roll - off. a digital inphase and quadrature modulator upcovert s a pair of dac input signal s to a n if frequency within the first nyquist zone of the dac programmed into a n nco . gain, phase, dc offset, and group delay adjustments can programmably predistort the dac input signals to improve lo feedthrough and unwanted sideband cancellation performance o f an analog quadrature modulator following the AD9154 in a transmitter signal chain. the AD9154 dac cores provide a differential curre nt output with a nominal full - scale current of 20 ma. the differential current outputs are optimized for integration with the analog devices adrf6720 - 27 wideband quadrature modulato r . the AD9154 has a mechanism for multich ip synchronization , a s well as a mechanism for achieving deterministic latency (latency locking). the latency for each dac remains constant from link establishment t o link establishment. the AD9154 makes use of the jesd204b subclass 1 sysref signal to establish multichip synchronization . the various functional blocks and the data interface must be set up in a specific sequence for proper operation (see the device setup guide section). this data sheet describes the various blocks of the AD9154 in detail, including descriptions of the jesd204b inter face, the control parameters, and the various registers used to set up and monitor the device. the recommended start - up routine reliably sets up the data link.
AD9154 data sheet rev. b | page 22 of 124 serial port operatio n the serial port interface (spi) is a flexible, sy nchronous serial communications port that allows easy interfacing with many industry - standard micro controllers and microprocessors. the interface facilitates read/write access to all registers that configure the AD9154 . msb first or lsb first transfer formats are supported. the sp i is configurable as a 4 - wire interface or a 3 - wire interface in which the input and output share a single - pin i/o, sdio . figure 36 . spi pins t here are two phases to a communication cycle with the AD9154 . phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first 16 sclk rising edges. the instruction word provides the serial port controller with information regarding the data transfer cycle, phase 2 of the communication cycle. the phase 1 instruction word defines whether the upcoming data transfer is a read or write, along with the sta rting register address for the following data transfer. a logic high on the cs pin , followed by a logic low , resets the serial port timing to the initial state of the instruction cycle. from this state, the next 16 rising sclk edges repr esent the instruction bits of the current input/output ( i/o ) operation. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the device and the system controller. phase 2 of the communication cycl e is a transfer of one or more data bytes. eight n sclk cycles are needed to transfer n bytes during the transfer cycle. registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word (ftw) and numer ically controlled oscillator (nco) phase offsets, which change only when the frequency tuning word ftw_update_req bit is set. data format the instruction byte cont ains the information shown in table 13. table 13 . serial port instruction word i 15 (msb) i[ 14:0 ] r/ w a[ 14:0 ] r/ w , bit 15 of the instruction word, determines whether a read or a write data transfer occurs after the instruction word write. logic 1 indicates a read operation, and logic 0 indicates a write operation. a14 to a0, bit 14 to bit 0 of the instruction word, determine the register accessed during the data transfer portion of the communication cycle. for multibyte transfers, a[14:0] is the starting address. the device generates the remaining register addresses based o n the address increment bit s . if the address increment bit s are set high (register 0x000, bit 5 and bit 2), multibyte spi writes start on a[ 1 4:0] and increment by 1 every eight bits sent/received. if the address increment bit s are set to 0, the address decrements by 1 every eight bits. serial port pin desc riptions serial clock (sclk) the serial clock pin synchronizes data to and from the device and runs the internal state machine s. the maximum frequency of sclk is specified in table 2 . all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. chip select ( cs ) an active low input starts a nd gates a communication cycle. it allows the use of more than one device on the same serial communications lines. the sdio pin goes to a high impedance state when this input is high. during the communication cycle, chip select must stay low. serial data i/o (sdio) this pin is a bidirectional data line. in 4 - wire mode, this pin acts as the data input and sdo acts as the data output. serial port options the serial port can support both msb first and lsb first data formats. t he lsb first bit s (regist er 0x000 , bit 6 and bit 1) control this functionality . the default is msb first ( the lsb first bit s = 0). when the lsb first bit s = 0 (msb first), the instruction and data bits must be written from msb to lsb. r/ w is followed by a[14:0] as the in struction word, and d[7:0] is the data - word. when the lsb first bit s = 1 (lsb first), the opposite is true. a[0:14] is followed by r/ w , which is subsequently followed by d[ 0:7 ]. the serial port supports a 3 - wire or 4 - wire interface. when the sdo active bits = 1 (register 0x000, bit 4 and bit 3), a 4 - wire interface with a separate input pin (sdio) and output pin (sdo) is used. when the sdo active bits = 0, the sdo pin is unused and the sdio pin is used for both input and output. 64 sclk 63 sdio 62 sdo 65 cs spi port 11389-027
data sheet AD9154 rev. b | page 23 of 124 multibyte data transfers can be performed as well. hold the cs pin low for multiple data transfer cycles (eight sclks) after the first data transfer word following the instruction cycle. the first eight sclks following the instruction cycle read fr om or write to the register provided in the instruction cycle. for each additional eight sclk cycles, the address is either incremented or decremented and the read/wri te occurs on the new register. set the direction of the address usi ng the address increme nt bit s (register 0x000 , b it 5 and bit 2). when the address increment bit s = 1, the multicycle addresses are incremented. when the address increment bit s = 0, the addresses are decremented. a new write cycle can always be initiated by bringing cs h igh and then low again. during writes to register 0x0000 only , the chip tests the first nibble following the address phase, ignoring the second nibble. this is completed independently from the lsb first bit and ensures that there are extra clock cycles following the soft reset bits (register 0x000, bit 0 and bit 7) . figure 37 . serial register interface timing, msb first, ad dress increment bits = 0 figure 38 . serial register interface timing , lsb first, address increment bits = 1 figure 39 . timing diagram for serial port register read figure 40 . timing diagram for serial port register write r/w a14 a13 a3 a2 a1 a0 d7 n d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle sclk sdio 11389-028 cs a0 a1 a2 a12 a13 a14 d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle sclk sdio 11389-029 cs r/w sclk sdio cs data bit n ? 1 data bit n t dv 11389-139 sclk sdio cs instruction bit 14 instruction bit 0 instruction bit 15 t scs t ds t dh t pwh t pwl 11389-140 t hcs
AD9154 data sheet rev. b | page 24 of 124 chip information register 0x003 to register 0x006 contain ch ip information, as shown in table 14. table 14 . chip information information description chip type the product is a high speed dac represented by a code of 0x04 in registe r 0 x 003. product id 8 msbs in register 0x005 and 8 lsbs in register 0x004. the product id is 0x91 5 4 . product grade register 0x006 , bits [7:4]. the product grade is 0x 8 . device revision register 0x006 , bits [3:0]. the device revision is 0x 9 .
data sheet AD9154 rev. b | page 25 of 124 device s etup guide follow these steps to properly set up the AD9154 : 1. set up the spi interface, power up necessary circuit blocks, make required writes to the configuration registers, and set up the dac c locks (see step 1: start up the dac ). 2. set the digital features of the AD9154 (see step 2: digital datapath ). 3. set up the jesd204b links (see step 3: transport layer ). 4. set up the physical layer of the serdes interface (see step 4: physical layer ). 5. set up the data link layer of the serdes interface (s ee step 5: data link layer ). 6. check for errors (see step 6 : error monitoring ) . 7. e nable any additional datapath features needed as described in table 19. a specific working start - up sequence example i s given in the example start - up sequence section. the register writes listed in table 15 to table 22 are necessary writes to se t up the AD9154 . consider printing out this setup guide and filling in the value column with app ropriate variable values for the conditions of the desired application. the v alue notation 0x withou t a specified value setting indicates register settings that must be filled in by the user. to fill in the unknown register values, select the correct settings fo r each variable listed in the variable column of tabl e 15 to table 22. the description column describes how to set variables , or provides a link to a section where this procedure is described. register settings with specified values are fixed settings to be used in all cases. a variable is noted by concatenating multiple terms. for example, pddacs is a variable corresponding to the value that is determined for register 0x011[6:3] in the device setup guide section. step 1: start up the dac this section de scribes how to set up the spi interface, power up necessary circuit blocks, as w ell as the required writes to the configuration registers, and how to set up the dac clocks. table 15 . power - up and dac initialization settings addr. b it no. value 1 variable description 0x000 0xbd soft reset. 0x000 0x3c deassert reset, set 4 - wire spi. 0x011 0x 7 0 power - up band gap. [6:3] pddacs pddacs = 0 if all four dacs are being used. if not, see the dac power - down setup section. 0x080 [7:6] pdclocks pdclocks = 0 if all four dacs are being used. if not, see the dac power - down setup section. 1 0x1 duty_en always set duty_en = 1 0x081 0x pdsysref pd sysref = 0x00 for subclass 1 . pdsysref = 0x10 for subclass 0. see the subclass setup section for details on subclass. 1 0x denotes a register value that the user must fill in. see the variable and description colu mns for information on selecting the appropriate register value. the registers in table 16 must be written to and the values changed from default f or the device to work correctly. these registers must be written t o after any soft reset, hard reset, or on a power - up. table 16 . required device configurations addr. value description 0x12d 0x8b digital datapath configuration 0x146 0x01 digital datapath configuration 0x333 0x01 jesd interface configuration
AD9154 data sheet rev. b | page 26 of 124 if using the optional dac pll, also set the registers in table 17. table 17 . optional dac pll configuration procedure addr. value 1 variable description 0x087 0x62 optimal dac pll loop filter settings 0x088 0xc9 optimal dac pll loop filter settings 0x089 0x0e optimal dac pll loop filter settings 0x08a 0x12 optimal dac pll cp settings 0x08d 0x7b optimal dac ldo settings for dac pll 0x1b0 0x00 power dac pll blocks when power machine disabled 0x1b5 0xc9 optimal dac pll vco settings 0x1b9 0x24 optimal dac pll calibration options settings 0x1bc 0x0d optimal dac pll block control settings 0x1be 0x02 optimal dac pll vco power control settings 0x1bf 0x8e optimal dac pll vco calibration settings 0x1c0 0x2a optimal dac pll lock counter length setting 0x1c1 0x2a optimal dac pll charge pump setting 0x1c4 0x7e optimal dac pll varactor settings 0x1c5 0x06 optimal dac pll vco settings 0x08b 0x lodivmode see t he dac pll setup section 0x08c 0x refdivmode see the dac pll setup section 0x085 0x bcount see the dac pll setup section variou s 0x lookupvals see the dac pll setup section 0x083 0x10 enable dac pll 2 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on selecting the approp riate register value. 2 verify that register 0x084[1] reads back 1 after enabling the dac pll to indicate that the dac pll has locked. step 2: digital data path the digital datapath selects interpolation mode and the data format . a dditional digital datapat h capabilities are shown in table 19. table 18 . digital datapath settings addr. bit no. value 1 variable description 0x112 0x interpmode select the interpolation mode; see the interpolation section. 0x110 0x 7 datafmt datafmt = 0 if twos complement; datafmt = 1 if unsigned binary. 1 0x denotes a register value that the user must fill in. see the variable and description columns for informati on on selecting the appropriate register value. there are a number of signal processing functions to be enabled if needed ; these are in addition to the interpolation mode . table 19. digital datapath signal processing functions fe ature default description digital modulation off modulates the data with a desired if carrier. see the digital datapath section. inverse sinc on improves pass - band flatness. see the digital datapath section. digital gain 0 db m ultiplies data by a factor to compensate inverse sinc usage or balance i/q amplitude. see the digital datapath section. phase adjust off used to balance i/ q phase. see the digital datapath section. dc offset off used to cancel lo leakage. see the digital datapath section. group delay 0 used to control overall latency. see t he digital datapath section. downstream protection off used to protect downstream components. see the digital datapath section. step 3: transport la yer this section desc ribes how to set up the jesd204b links. the desired jesd204b operating mode determines the parameters . see the jesd204b setup section for details. table 20 . transport layer settings addr. bit no. value 1 var iable description 0x200 0x00 power up the interface. 0x201 0x unusedlanes see the jesd204b setup section. 0x300 0x 6 checksummode see the jesd204b setup section . 3 duallink see the jesd204b setup section. 2 currentlink see the jesd204b setup section. 0x450 0x did set did to match the device id sent by the transmitter. 0x4 51 0x bid set bid to match the bank id sent by the transmitter. 0x452 0x lid set lid to match the lane id sent by the transmitter. 0x453 0x 7 scrambling see the jesd204b setup section. [4:0] l ? 1 2 se e the jesd204b setup section. 0x454 0x f ? 1 2 see the jesd204b setup section. 0x455 0x k ? 1 2 see the jesd204b setup section. 0x456 0x m ? 1 2 see the jesd204b setup section. 0x457 0x n ? 1 2 n = 16. 0x458 0x 5 subclass see the jesd204b setup section. [4:0] np ? 1 2 np = 16.
data sheet AD9154 rev. b | page 27 of 124 addr. bit no. value 1 var iable description 0x459 0x [7:5] jesdver jesdver = 1 for jesd204b, jesdver = 0 for jesd204a. [4:0] s ? 1 2 see the jesd204b setup section. 0x45a 7 0x hd see the jesd204b setup section. [4: 0] cf cf = 0 0x45d 0x lane0checksum see the jesd204b setup section. 0x46c 0x lanes deskew lanes. 0x476 0x f see the jesd204b setup section. 0x47d 0x lanes enable l anes. see the jesd204b setup section. 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on selecting the appropriate register value. 2 this jesd204b link parameter is programmed in n ? 1 notation as noted. for example, if the setup requires l = 8 (8 lanes per link), program l ? 1 or 7 into register 0x453 , bits [4:0]. if using dual lin k, perform writes from register 0x300 to register 0x47d with curren tlink = 0 , and then repeat the same set of regist er writes with currentlink = 1. write to register 0x200 and register 0x201 only once . step 4: physical lay er this section describes how to set up the physical layer of the serdes interface. in this section , the input termination settings are configured along with the cdr sampling and serdes pll. table 21 . device configurations and physical layer settings addr. bit no. value 1 variable description 0x2a7 0x01 autotun e phy setting 0x2ae 0x01 autotune phy setting 0x314 0x01 serdes spi configuration 0x230 0x 5 halfrate set up the cdr; see the serdes clocks setup section [4:2] 0x2 [2:1] ovsmp set up the cdr; se e the serdes clocks setup section 0x206 0x00 reset the cdr 0x206 0x01 release the cdr reset 0x289 0x 2 1 serdes pll configuration [1:0] plldiv set the cdr oversampling for pll; see the serdes clocks setup section 0x284 0x62 optimal serdes pll loop filter 0x285 0xc9 optimal serdes pll loop filter 0x286 0x0e optimal serdes pll loop filter 0x287 0x12 optimal serdes pll cp 0 x28a 0x7b optimal serdes pll vco ldo 0x28b 0x00 optimal serdes pll pd 0x290 0x8 9 optimal serdes pll vco 0x291 0x4c optimal serdes pll vco 0x294 0x24 optimal serdes pll cp 0x296 0x1b optimal serdes pll vco 0x297 0x0d optimal serdes pll vco 0x299 0x02 optimal s erdes pll pd 0x29a 0x8e optimal serdes pll vco 0x29c 0x2a optimal serdes pll cp 0x29f 0x7e optimal serdes pll vco 0x2a0 0x0 6 configure serdes pll vco 0x280 0x01 enable serdes pll 2 0x268 0x [7:6] eqmode see the equalization mode setup section [5:0] 0x22 required value (default) 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on selecting the appropriate register value. 2 veri fy that register 0x281, bit 0 reads back 1 after enabling the serdes pll to indicate that the serdes pll has locked.
AD9154 data sheet rev. b | page 28 of 1 24 step 5: data link la yer this section describes how to set up the data link layer of the serdes interface. this section deals with sy sref processing, setting deterministic latency, and establishing the link. table 22 . data link layer settings address bit no. value 1 variable description 0x301 0x subclass see the jesd204b setup section. 0x304 0x lmfcdel see the link latency setup section. 0x305 0x lmfcdel see the link latency section. 0x306 0x lmfcvar see the link latency setup section. 0x307 0x lmfcvar see the link latency setup section. 0x03a 0x01 set sync mode = one - shot sync; see the syncing lmfc signal s section for other sync options. 0x03a 0x81 enable the sync machine. 0x03a 0xc1 arm the sync machine. sysref if subclass = 1, ensure that at least one sysref edge is sent to the device. 2 0x308 to 0x30b 0x xbarvals if remapping lanes, set up crossbar; see the crossbar setup section. 0x334 0x invlanes invert the polarity of desired logical lanes. bit x of invlanes must be a 1 for each logical lane x to invert. 0x300 0x enable the links. 6 check sum mode see the jesd204b setup section. 3 duallink see the jesd204b setup section. [1:0] enlinks enlinks = 3 if duallink = 1 (enables link 0 and link 1); enlinks = 1 if duallink = 0 (enables link 0 only). 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on selecting the appropriate register value. 2 verify that register 0x03b, bit 3 reads back 1 after s ending at least one sysref edge to the device to indicate that the lmfc sync machine has properly locked. step 6 : error monitoring for jesd204b error monitoring, see the jesd204b error monitoring section. for other error checks, see the interrupt request operation section . dac pll setup this section explains how to select appropriate lodivmode, refdivmode, and bcount in the step 1: start up th e dac section. these parameters depend on the desired dac clock frequency (f dacclk ) and dac reference clock frequency (f ref ). when using the dac pll, the reference clock signal is applied to the clk differential pins, pin 2 and pin 3 . table 23 . dac pll lodivmode settings dac frequency range (mhz) lodivmode , register 0x08b[1:0] 1500 to 2 4 00 1 750 to 1500 2 420 to 750 3 table 24 . dac pll refdivmode settings dac pll reference frequency (f ref ) (mhz) divid e by ( refdivfactor) refdivmode , register 0 x 08 c[ 2:0 ] 35 to 80 1 0 80 to 160 2 1 160 to 320 4 2 320 to 640 8 3 640 to 1000 16 4 the vco frequency (f vco ) is related to the dac clock frequency according to the following equation: f vco = f dacclk 2 lodivm ode + 1 where 6 ghz f vco 12 ghz. bcount must be between 6 and 127 and is calculated based on f dacclk and f ref as follows: bcount = floor (( f dacclk )/(2 f ref / refdivfactor )) where refdivfactor = 2 refdivmode (see table 24). final ly, to finish configuring the dac pll, set the vco control registers up as described in table 80 based on the vco frequency (f vco ). for more information on the dac pll, see the dac input clock configuratio ns section.
data sheet AD9154 rev. b | page 29 of 124 interpolation the transmit path can use zero to three cascaded interpolation filters, which each provide a 2 increase in output data rate and a low - pass function. table 25 shows the different i nterpolation modes and the respective usable bandwidth , along with the maximum f data rate attainable. table 25 . interpolation modes and their usable bandwidth in terpolation mode interpmode usable bandwidth 1 (bypass) 0 x 00 0.5 f d ata 2 0 x 01 0.4 f data 4 0 x 03 0.4 f data 8 0 x 04 0.4 f data the usable bandwidth is defined for 1, 2, 4, and 8 modes as the frequency band over which the filters have a pass - band ripple of less than 0.001 db and an image rejection of greater than 85 db. for more information, see the interpolation section. jesd204b setup this section explains how to select a jesd204b operating mode f or a desired application. this in turn defines appropriate values for checksummode, unu sedlanes, duallink, currentlink, scrambling, l, f, k, m, n, np, subclass, s, hd, lane0checksum, and lanes needed for the step 3: transport layer sectio n. note that duallink, scrambling, l, f, k, m, n, np, s, hd, and subclass must have the same settings on the transmit side. for a summary of how a jesd204b system works and what each parameter mean s , see the jesd204b serial data interface section. available operating modes table 26 . jesd204b operating modes (single link only) mode parameter 0 1 2 3 m (converter count) 4 4 4 4 l (lane count) 8 8 4 2 s ((samples per converter) per frame) 1 2 1 1 f ((octets per frame) per lane) 1 2 2 4 table 27. jesd204b operating modes ( single or dual link) mode parameter 4 5 6 7 9 10 m (converter count) 2 2 2 2 1 1 l (lane count) 4 4 2 1 2 1 s ((samples per converter) per frame) 1 2 1 1 1 1 f ((octets per frame) per lane) 1 2 2 4 1 2 for a partic ular application, the number of converters to use (m) and the f data (datarate) are known. the lanerate and number of lanes (l) can be traded off as follows: datarate = ( dacrate )/( interpolationfactor ) lanerate = (20 datarate m )/ l where lanerate is speci fied in table 4 . octets per frame per lane (f) and samples per convertor per frame (s) define how the data is packed. if f = 1, the high density (hd) setting must be set to 1 (hd = 1 ). otherwise, set hd = 0 . both the c onverter res olution (n) and the bits per sample (np) must be set to 16. k must be set to 32 for mode 0 , mode 4 and mode 9 . other modes may use either k = 16 or k = 32. duallink duallink sets up two independent jesd204b links ; each link can be reset independently. if duallink i s desired, set it to 1; if a single link is desired, set duallink to 0. note that link 0 and link 1 must have identical parameters. the operating modes available when using dual link mode are shown in tabl e 26 . in addition to these operating modes, the modes in table 27 may also be used when using single link mode. scrambling scrambling is a feature that makes the spectrum of the link data independent. this avoids spectral peaking and provides some protection against data dependent errors caused by frequency selective effects in the electrical interface. set scrambling to 1 if scrambling is being used, or to 0 if it is not. subclass subclass determines whether the l atency of the device is deterministic, meaning it requires an external synchronization signal. see the subclass setup section for more information. currentlink to configure link 0 or link 1, s et currentlink to eith er 0 or 1 , respectively. lanes lanes enable s and deskew s particular lanes in two thermometer coded registers. lanes = (2 l ) ? 1 unusedlanes unusedlanes turn s off unused circuit blocks to save power. each physical lane not being used (serdinx) must be powe red off by writing a 1 to the corresponding bit of register 0x201. for example, if using mode 6 in dual link mode and sending data on serdin0, serdin1, serdin4, and serdin5, set unusedlanes = 0xcc to power off physical lane 2, physical lane 3, physica l lane 6, and physical lane 7 .
AD9154 data sheet rev. b | page 30 of 124 checksummode checksummode must match the checksum mode used on the transmit side. if the checksum used is the sum of fields in the link configuration table, checksummode = 0. if summing the registers containing the packed link configuration fields, checksummode = 1. for more information on the how to calculate the two checksum modes, see the lane0checksum section. lane0checksum lane0checksum is used for error checking purposes to ensure that the transmitter is set up as expected. if checksummode = 0, the checksum is the lower 8 bits of the sum of the l ? 1, m ? 1, k ? 1, n ? 1, np ? 1, s ? 1, scrambling, hd, subclass, and jesdver variables. if checksummode = 1, lane0checksum is the lower 8 bits of the sum of register 0x450 to register 0x45a. select whether to sum by fields or by registers, matching the setting on the transmitter. dac power-down setup as described in the step 1: start up the dac section, pddacs must be set to 0 if all four converters are being used. if fewer than four converters are in use, the unused converters can be powered down. use table 28 determine which dacs are powered down based on the number of converters per link (m) and whether the device is in duallink mode. table 28. dac power-down configuration settings m (converters per link) duallink dacs to power down pddacs 0 1 2 3 1 0 0 1 1 1 0b0111 1 1 0 1 1 0 0b0110 2 0 0 0 1 1 0b0011 2 1 0 0 0 0 0b0000 4 0 0 0 0 0 0b0000 when using m = 1 in duallink mode, set the i_to_q bit high to ensure data entering dac dual b is sent to the dac 3 output. pdclocks if both dacs in dac dual b (dac2 and dac3) are powered down, the clock for dac dual b can be powered down. in this case, register 0x080, bits[7:6] = 0x1; otherwise, register 0x080, bits[7:6] = 0x0. serdes clocks setup this section describes how to select the appropriate halfrate, ovsmp, and plldiv settings in the step 4: physical layer section. these parameters depend solely on the lane rate. the lane rate is established in the jesd204b setup section. table 29. serdes lane rate configuration settings lane rate (gbps) (see table 4) halfrate ovsmp plldiv cdr oversampling mode 0 1 2 cdr full rate mode 0 0 1 cdr half rate mode 1 0 0 halfrate and ovsmp set how the clock detect and recover (cdr) circuit samples. see the serdes pll section for an explanation of how this circuit blocks works and the role of plldiv in the block. equalization mode setup set eqmode = 1 for a low power setting. select this mode if the insertion loss in the printed circuit board (pcb) is less than 12 db. for insertion losses greater than 12 db but less than 17.5 db, set eqmode = 0. see the equalization section for more information. link latency setup this section describes the steps necessary to guarantee multichip deterministic latency in subclass 1 and guarantee synchronization of links within a device in subclass 0. use this section to fill in lmfcdel, lmfcvar, and subclass in the step 5: data link layer section. for more information, see the syncing lmfc signals section. subclass setup the AD9154 supports jesd204b subclass 0 and subclass 1 operation. subclass 1 subclass 1 mode achieves deterministic latency and allows the synchronization of links to within the limits called out in table 7. it requires an external sysref signal accurately phase aligned to the dac clock. subclass 0 subclass 0 mode does not require any signal on the sysref pins; leave these pins disconnected. subclass 0 still requires that all lanes arrive within the same lmfc cycle and the dual dacs must be synchronized to each other (they are synchronized to an internal clock instead of the sysref signal when in subclass 0 mode). set subclass to 0 or 1 as desired. link delay setup lmfcvar and lmfcdel impose delays such that all lanes in a system arrive in the same lmfc cycle. the unit used internally for delays is the period of the internal processing clock (pclock), with a rate 1/40 th of the lane rate. delays that are not in pclock cycles must be converted before they are used. some useful internal relationships are defined below: pclockperiod = 40 /lanerate
data sheet AD9154 rev. b | page 31 of 124 the pclockperiod is used to convert from time to pclock cycles when needed. pclockfactor = 4/ f (frames per pclock) the pclockfactor is used to convert from units of pclock cycles to f rame c lock cycles, which is required to set lmfcdel in subclass 1 . pclockspermf = k / pclockfactor (p clocks per lmfc c ycle) where pclockspermf is the number of pclock cycles in a multiframe cycle. the values for pclockfactor and pclockpermf are given per jesd 204b mode in table 30 and table 31. table 30 . pclockfactor and pclockpermf per lmfc jesd204b mode id 0 1 2 3 pclockfactor 4 2 2 1 pclockpermf (k = 32) 8 16 16 32 pclockpermf (k = 16) n ot applicable 8 8 16 table 31 . pclockfactor and pclockpermf per lmfc jesd204b mode id 4 5 6 7 9 10 pclockfactor 4 2 2 1 4 2 pclockpermf (k = 32) 8 16 16 32 8 16 pclockpermf (k = 16) n/a 1 8 8 16 n/a 1 8 1 n/a means not applicable. with known delays lm fcvar and lmfcdel can be calculated directly w ith information about all the system delays . rxfixed (the fixed receiver delay in pclock cycles) and rxvar (the variable receiver delay in pclock cycles) are found in ta ble 8 . txfi xed (the fixed transmitter delay in pclock cycles) and txvar (the variable receiver delay in pclock cycles) can be found in the data sheet of the transmitter used. pcbfixed (the fixed pcb trace delay in pclock cycles) is extracted from the soft ware. b ecause pcbfixed is generally much s maller than a pclock cycle, it c an be omitted. for both the pcb and tra nsmitter delays, convert the delays into pclock cycles. for each lane , mindelaylane = floor ( rxfixed + txfixed + pcbfixed ) fal l_count_d elaylane = ceiling ( rxfixed + rxvar + txfixed + txvar + pcbfixed )) where, across lanes, links, and devices: mindelay lane is the minimum of all mindelaylane values. fall_count_d elay is the maximum of all fall_count_d elaylane values. for safety, add a guard band of 1 pclock cycle to each end of the link delay , as shown in the following equations: lmfcvar = ( fall_count_d elay + 1) ? ( mindelay ? 1 ) note that if lmfcvar must be more than 10, the AD9154 cannot tolerate the variable delay in the system. for subclass 1 , lmfcdel = (( mindelay ? 1) pclockfactor ) % k for sub class 0 , lmfcdel = ( mindelay ? 1) % pclockpermf program the same lmfcdel and lmfcvar across all links and devices. see the link delay setup example, with known delays section for an example calculation. without kn own delays if comprehensive delay information is not available or known, the AD9154 can read back the link latency between the lmfc rx and the last arriving l mfc boundary in pclock cycles. use t his information to calculate lmfcvar and lmfcdel. for each link on each device, 1. power up the board. 2. follow the steps in table 15 through table 22 in the device setup guide section. 3. set the subclass and perform a sync. for a one - shot sync, perform the writes in table 32 . see the syncing lmfc signals section for alternate sync modes . 4. record dyn_link_latency_ 0 (register 0 x 302 ) as a value of delay for that link and power cycle. 5. record dyn_link_latency_ 1 (register 0 x 303 ) as a value of delay for that link and power cycle. repeat step 1 through step 5 twenty times for each devi ce in the system. keep a single list of the delay values across all runs and devices. table 32 . register configuration and procedure for one -s hot sync addr. bit. no. value 1 variable description 0x301 0x subclass set subclass 0x0 3a 0x01 set sync mode = one - shot sync 0x03a 0x81 enable the sync machine 0x03a 0xc1 arm the sync machine sysref if subclass = 1, ensure that at least one sysref edge is sent to the device 0x300 0x enable the links 6 chksmmd see the jesd204b setup section 3 dual link see the jesd204b setup section [1:0] enlinks enlinks = 3 if in duallink mode to enable link 0 and link 1; enlinks = 1 if not in dualli nk mode to enable link 0 1 0x denotes a register value that the user must fill in. see the variable and description columns for information on selecting the appropriate register value.
AD9154 data sheet rev. b | page 32 of 124 use t he list of delay values to calculate lmfcdel and lmfcvar, but not e that some of the delay values may need to be remapped first . the maximum possible value for dyn_link_latency_x is one less than the number of pclocks in a multiframe (pclockspermf). a roll over condition may be encountered, meaning the set of recorded d el ay values may roll over the edge of a multiframe. if so, delay values may be near both 0 and pclockspermf . if this occurs, add pclockspermf to the set of values near 0 . for example, for delay value readbacks of 6, 7, 0, and 1, the 0 and 1 delay values must be remapped to 8 and 9, making the new set of delay values 6 , 7 , 8 , and 9 . across power cycles, links, and devices , ? mindelay is the minimum of all delay measurements . ? fall_count_d elay is the maximum of all delay measurements . for safety, add a guard band of 1 pclock cycle to each end of the link delay and calculate lmfcvar and lmfcdel with the following equation: lmfcvar = ( fall_count_d elay + 1) ? ( mindelay ? 1) note that if lmfcvar must be more than 10, the AD9154 cannot tolerate the variable delay in the system. for subclass 1 , lmfcdel = (( mindelay ? 1) pclockfactor ) % k for sub class 0 lmfcdel = ( mindelay ? 1) % pclockpermf program the same lmfcdel and lmfcvar across all links and devices. see the link delay setup example, without known delay section for an example calculation . crossbar setup register s 0 x 308 to register 0 x 30 b allow arbitrary mapping of physical lanes (serdinx) to logical lanes used by the serdes deframers. table 33 . crossbar registers address bits logical lane 0x308 [2:0] xbarval0 0 x 308 [5:3] xb arval 1 0x309 [2:0] xbarval 2 0 x 309 [ 5:3 ] xbarval 3 0x30a [2:0] xbarval 4 0 x 30a [ 5:3 ] xbarval 5 0 x 30b [ 2:0 ] xbarval 6 0 x 30b [ 5:3 ] xbarval 7 write each xbarvaly with the number (x) of the desired physical lane (serdinx) from which to get data. by default, all logical lanes use the corresponding physical lane as their data source. for example, by default , xbarval0 = 0 , meaning logical lane 0 receives data from physical lane 0 (serdin0). if instead the user wants to use serdin4 as the source for logical lan e 0, the user must write xbarval0 = 4.
data sheet AD9154 rev. b | page 33 of 124 jesd204b serial data interface jesd204b overview the jesd204b setup section explains how to select a jesd204b operating mode. this section presents an overview of the inner workings of the AD9154 jes d204b receiver implementation. the AD9154 has eight jesd204b data ports that receive data. the e ight jesd204b ports ca n be configured as part of a single jesd 204 b link or as part of two separate jesd 204 b links (dual link mode) that share a single system reference (sysref) and device clock (clk). the jesd204b hardware protocol stack consists of three layers: the physical layer, the data link layer, and the transport layer. these sections of the hardware are described in subsequent sections, including information for configuring every aspect of the interface. figure 41 shows the co mmunication layers implemented in the AD9154 serial data int erface to recove r the clock and deserialize, descramble, and deframe the data before it is sent to the digital signal processing section of the device. the physical layer establishes a reliable channel between the transmitter and the receiver, the data link layer unpacks the data into frames of octets and descrambles the data, and the transport layer receives the descrambled jesd204b frame s and converts them to dac input samples. a number of jesd204b parameters (l, f, k, m, n, np, s, and hd) define how the data is packed and instruct the device on how to turn the serial data into samples. these parameters are defined in detail in the transport layer section. only certain combinations of parameters are supported. each supported combination is called a jesd204b operating mode. in total, there are 10 single link modes supported by the AD9154 , as described in table 34 . in dual link mode, there are six supported modes, as described in table 35. each of these tables shows the ass ociated clock rates when the lane rate is 10 gbps. for a particular application, the number of converters to use (m) and the datarate are known. the lanerate and number of lanes (l) can be traded off as follows: datarate = ( dacrate )/( interpolationfactor ) l anerate = (20 datarate m )/ l where lanerate must be between 1.42 gbps and 10.64 gbps. a chieving and recovering synchronization of the lanes is very important. to simplify the interface to the transmitter , the AD9154 designates a master synchronization signal for ea ch jesd204b link. in single link mode, syncout0 is the master signal for all lanes; in dual link mode, syncout0 is the master signal for link 0 , a nd syncout1 is used as the master signal for link 1. if any lane in a link loses synchronization, a resynchroniza - tion request is sent to the transmitter via the syncout signal of the link. the transmitter stops sending data and instead sends synchronization characters to all lanes in that link until resynchronization is achieved. figure 41 . functional block diagram of serial link receiver table 34 . single link jesd204b operating modes mode parameter 0 1 2 3 4 5 6 7 9 10 m (converter counts) 4 4 4 4 2 2 2 2 1 1 l (lane counts) 8 8 4 2 4 4 2 1 2 1 s (samples per converter per frame) 1 2 1 1 1 2 1 1 1 1 f (octets per frame per lane) 1 2 2 4 1 2 2 4 1 2 example clocks for 10 gbps la ne rate pclock (mhz) 250 250 250 250 250 250 250 250 250 250 frame clock (mhz) 1000 500 500 250 1000 500 500 250 1000 500 sample clock (mhz) 1000 1000 500 250 1000 1000 500 250 1000 500 1 1389-003 deserializer data link layer transport layer serdin0 sysref serdin7 dual a i data[15:0] dual a q data[15:0] dual b q data[15:0] dual b i data[15:0] to dac syncout1 syncout0 physical layer deserializer frame to samples qbd/ descrambler
AD9154 data sheet rev. b | page 34 of 124 table 35. dual link jesd204b operating modes for link 0 and link 1 mode parameter 4 5 6 7 9 10 m (converter counts) 2 2 2 2 1 1 l (lane counts) 4 4 2 1 2 1 s (samples per converter per frame) 1 2 1 1 1 1 f (octets/frame per lane) 1 2 2 4 1 2 example clock for 10 gbps lane rate pclock (mhz) 250 250 250 250 250 250 frame clock (mhz) 1000 500 500 250 1000 500 sample clock (mhz) 1000 1000 500 250 1000 500 f igure 42. deserializer block diagram physical layer the physical layer of the jesd204b interface, hereafter referred to as the deserializer, has eight identical channels. each channel consists of the terminators, an equalizer, a cdr circuit, and the 1:40 demux function (see figure 42). jesd204b data is input to the AD9154 via the serdinx 1.2 v differential input pins as per the jesd204b specification. power-down unused phys note that any unused and enabled lanes unnecessarily consume extra power. each lane that is not in use (serdinx) must be powered off by writing a 1 to the corresponding bit of phy_pd (register 0x201). interface power-up and input termination before using the jesd204b interface, it must be powered up by setting register 0x200[0] = 0. in addition, each physical lane that is not being used (serdinx) must be powered down. to do so, set the corresponding bit x for physical lane x in register 0x201 to 0 if the physical lane is being used, and to 1 if it is not being used. the AD9154 autocalibrates the input termination to 50 . register 0x2a7 controls autocalibration for phy 0, phy 1, phy 6, and phy 7. register 0x2ae controls autocalibration for phy 2, phy 3, phy 4, and phy 5. the phy termination autocalibration routine is shown in table 36. table 36. phy termination autocalibration routine address value description 0x2a7 0x01 autotune phy terminations 0x2ae 0x01 autotune phy terminations the input termination voltage of the dac is sourced externally via the v tt pins (pin 21, pin 25, pin 42, and pin 46). set v tt by connecting it to svdd12. it is recommended that the jesd204b inputs be ac-coupled to the jesd204b transmit device using 100 nf capacitors. receiver eye mask the AD9154 complies with the jesd204b specification regarding the receiver eye mask and can capture data that complies with this mask without equalization. with equalization enabled, the AD9154 can reliably capture from signals with much smaller eye openings. figure 43 shows the receiver eye mask normalized to the data rate interval with a 600 mv v tt swing. see the jesd204b specification for more information regarding the eye mask and permitted receiver eye opening. figure 43. receiver eye mask equalizer cdr 1:40 deserializer from serdes pll spi control termination serdinx 11389- 525 55 0 ?55 ?525 amplitude (mv) 0 0.5 1.00 0.35 0.65 time (ui) lv-oif-11g-sr tx eye mask (3.125mbps ui 12.5gbps) 11389-006
data sheet AD9154 rev. b | page 35 of 124 equalization to compensate for signal integrity distortions for each phy c hannel due to insertion loss caused by pcb trace characteristics , the AD9154 employs an easy to use, low power equalizer on each jesd204b channel. the AD9154 equalizers can compensate for in sertion losses far greater than required by the jesd204b specification. the equalize rs have two modes of operation determined by the eq_power_mode register setting in register 0x268 , bits [7:6]. in low power mode (register 0x268 , bits [7:6] = 2b01) and operating at the maximum lane rate, the equalizer can compensate f or up to 12 db of insertion loss. in normal mode (register 0x268 , bits [7:6] = 2b00), the equalizer can compensate for up to 17.5 db of in sertion loss. this performance is shown in figure 44 as an overlay to the jesd204b specification for insertion loss. figure 44 shows the equalization performance at 10.0 gb ps, near the maximum baud rate for the AD9154 . figure 45 and figure 46 are provided as points of reference for hardware designers and show the insertion loss for various lengths of well laid out stripline and microstrip t ransmission lines on fr - 4 material . low power mode is recommended if the insertion loss of the jesd204b pcb channels is less than that of the most lossy supported channel for lower power mode (shown in figure 44 ). if the insertion loss is greater than th at, but still less than that of the most lossy supported channel for normal mode (shown in figure 44 ), use normal mode. at 10 gbps operation, the equalize r in normal mode consumes about 4 mw more power per lane used than in low power equalize r mode. note that either mode can be used in conjunction with transmitter pree mphasis to ensure functionality and/or to optimize for power. figure 44 . insertion loss allowed figure 45 . insertion loss of 50 ? stripl ines on fr - 4 figure 46 . insertion loss of 50 ? microstrips on fr - 4 insertion loss ( db ) frequency (ghz) 0 2 4 6 8 10 12 14 16 18 20 22 24 5.0 7.5 2.5 AD9154 allowed channel loss (normal mode) AD9154 allowed channel loss (low power mode) jesd204b spec allowed channel loss example of jesd204b compliant channel example of AD9154 compatible channel (low power mode) example of AD9154 compatible channel (normal mode) 1 1389-339 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 1 2 3 4 5 6 7 8 9 10 a ttenu a tion (db) frequenc y (ghz) s tr iplin e = 6 ? s tr iplin e = 10 ? s tr iplin e = 15 ? s tr iplin e = 20 ? s tr iplin e = 25 ? s tr iplin e = 30 ? 1 1389-008 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 1 2 3 4 5 6 7 8 9 10 a ttenu a tion (db) frequenc y (ghz) 6? m i c r o s t ri p 1 0 ? m i c r o s t ri p 1 5 ? m i c r o s t ri p 2 0 ? m i c r o s t ri p 2 5 ? m i c r o s t ri p 3 0 ? m i c r o s t ri p 1 1389-009
AD9154 data sheet rev. b | page 36 of 124 clock multiplication relationships the following clocks rates are used throughout the rest of the jesd204b section. the relations hip between any of the clocks can be derived from the following equations: datarate = ( dacrate )/( interpolationfactor ) lanerate = (20 datarate m )/ l byterate = lanerate /10 where: m is the jesd 204 b parameter for converters per link. l is the jesd204b par ameter for lanes per link. f is the jesd 204 b parameter for octets per frame per lane. this comes from 8 - bit/ 10 - bit encoding, where each byte is represented by 10 bits. pclockrate = byterate /4 the processing clock is used for a quad - byte decoder. framerate = byterate / f where f is defined as (bytes per frame) per lane. pclockfactor = framerate / pclockrate = 4/ f serdes pll functional overview of the serdes pll the independent serdes pll uses integer - n techniques to achieve clock synthesis. the entire serdes p ll is integrated on chip, including the vco and the loop filter. the serdes pll vco operates over the range of 5.65 ghz to 12 ghz. in the serdes pll, a vco divider block divides the vco clock by 2 to generate a 2.825 ghz to 6 ghz quadrature clock for the deserializer cores. this clock is the input to the cdr block described in the clock and data recovery section. the reference clock to the serdes pll i s always running at a frequency of f ref = 1/40 of the lane rate = pclockrate. this clock is divided by a divfactor to deliver a clock to the pfd block that is between 35 mhz and 80 mhz. table 37 includes the respective serdes_pll_div_mode register settings for each of the desir ed divfactor options available. table 37 . serdes pll divider settings lanerate (gbps) (see table 4 ) divide by (divfactor) spi_cdr_oversamp register 0x289 , bits [ 1:0 ] cdr oversampling mode 1 2 cdr full rate mode 2 1 cdr half rate mode 4 0 register 0x280 controls the synthesizer enable and recalibration. to enable the serdes pll, first set the pll divider register according to table 37 , then enable the serde s pll by writing register 0x280, bit 0 to 1 . confirm that the serdes pll is working by reading register 0x281. if register 0x281, bit 0 = 1, the serdes pll is locked. if register 0x281, bit 3 = 1, the serdes pll is successfull y calibrated. if reg ister 0x281, bit 4 or register 0x281, bit 5 are high, the pll hit s the upper or lower end of its calibration band and must be recalibrated by writing 0 and then 1 to register 0x280, bit 2 . serdes pll fixed register wr ites to optimize the serdes pll across all operating conditions, the following register writes to the following locations are recommended : 0x284, 0x285, 0x286, 0x287, 0x28a, 0x28b, 0x290, 0x291, 0x294, 0x296, 0x297, 0x299, 0x29a, 0x29c, 0x29f , and 0x 2a0 as shown in tab le 21. serdes pll irq serdes pll lock a nd lost signals are available as irq events. use register 0x01f , bit 3 and bit2 to enable these signals, and then use register 0x023 , bit 3 and bit 2 to read back their statuses and reset the irq signals. see the interrupt request operation section for more information. figure 47 . serdes pll synthesizer block diagram including vco divider block lc vco 5.65ghz to 12ghz charge pump pfd 80mhz max up down f ref bit rate 40 3.2ma calibration control bits r1 c1 r3 c2 c3 vco ldo 2 80 2.825ghz to 6ghz output i q divfactor (1, 2, 4) 11389-144
data sheet AD9154 rev. b | page 37 of 124 clock and data recovery the deserializer is equipped with a cdr circuit. instead of recovering the clock from the jesd204b serial lanes, the cdr recovers the clocks from the serdes pll. the 2.825 ghz to 6 ghz output from the serdes pll, shown in figure 47, is the input to the cdr. select a cdr sampling mode to generate the lane rate clock inside the device. if the desired lane rate is greater than 5.65 ghz, half rate cdr operation must be used. if the desired lane rate is less than 5.65 ghz, disable half rate operation. if the lane rate is less than 2.825 ghz, disable half rate and enable 2 oversampling to recover the appropriate lane rate clock. table 38 breaks down the cdr sampling settings that must be set dependent on the lanerate. table 38. cdr operating modes lanerate (gbps) (see table 4) halfrate, register 0x230, bit 5 cdr_oversamp, register 0x230, bit 1 cdr oversampling mode 0 1 cdr full rate mode 0 0 cdr half rate mode 1 0 the cdr circuit synchronizes the phase used to sample the data on each serial lane independently. this independent phase adjustment per serial interface ensures accurate data sampling and eases the implementation of multiple serial interfaces on a pcb. after configuring the cdr circuit, reset it and then release the reset by writing 1 and then 0 to register 0x206, bit 0. data link layer the data link layer of the AD9154 jesd204b interface accepts the deserialized data from the phys and deframes and descrambles them so that data octets are presented to the transport layer to be put into dac samples. the architecture of the data link layer is shown in figure 48. it consists of a synchronization fifo for each lane, a crossbar switch, a deframer, and descrambler. the AD9154 can operate as a single link or dual link, high speed jesd204b serial data interface. when operating in dual link mode, configure both links with the same jesd204b parameters because they share a common device clock and system reference. all eight lanes of the jesd204b interface handle link layer communications such as code group synchronization, frame alignment, and frame synchronization. the AD9154 decodes 8-bit/10-bit control characters, allowing marking of the start and end of the frame and alignment between serial lanes. each AD9154 serial interface link can issue a synchronization request by setting its syncout0 / syncout1 signal low. the synchronization protocol follows section 4.9 of the jesd204b standard. when a stream of four consecutive /k/ symbols is received, the AD9154 deactivates the synchronization request by setting the syncout0 / syncout1 signal high at the next internal lmfc rising edge. then, it waits for the transmitter to issue a lane alignment sequence (ilas). during the ilas sequence, all lanes are aligned using the /a/ to /r/ character transition as described in the jesd204b serial link establishment section. elastic buffers hold early arriving lane data until the alignment character of the latest lane arrives. at this point, the buffers for all lanes are released and all lanes are aligned (see figure 49). figure 48. data link layer block diagram 11389-011 lane 0 deserialized and descrambled data lane 7 deserialized and descrambled data lane 0 data clock lane 7 data clock serdin0 fifo serdin7 fifo cross bar switch pclk data link layer spi control sysref syncoutx descramble 10-bit/8-bit decode system clock phase detect lane0 octets lane7 octets quad byte deframer (qbd)
AD9154 data sheet rev. b | page 38 of 124 figure 49 . lane alignment during ilas jesd204b serial link estab lishment a brief summary of the high speed serial link establishment process for subclass 1 is provided. see section 5.3.3 of the jesd 204 b specifications document for complete details. step 1 : code group synchronization each receiver must locate k (k28.5) characters in its input data stream. after four consecutive k characters are detected on all link lanes, the receiver block deasserts the syncoutx signal to the transmitter block at the lmfc edge. the transmitter captures the change in t he syncoutx signal, and at a future transmitter lmfc rising edge, starts the initial ilas . step 2 : initial lane alignment sequence the main purposes of this phase are to align all the lanes of the link and verify the parameters of the li nk. before the link is established, write each of the link parameters to the receiver device to designate how data is sent to the receiver block. the ilas consists of four or more multiframes. the last characte r of each multiframe is a multiframe alignment character, /a/. the first, third, and fourth multiframes are populated with predetermined data values. note that section 8.2 of the jesd204b specifications document describes the data ramp expected during ilas. by default, the AD9154 does not require th is ramp. register 0x47e[0] can b e set high to require the data ramp. the deframer uses the final /a/ of each lane to align the ends of the multiframes within the receiver. the second multiframe cont ains an r (k.28.0), q (k.28.4), and then data corresponding to the link parameters. additional multiframes can be added to the ilas if needed by the receiver. by default, the AD9154 uses four mult iframes in the ilas (this can be changed in register 0x478). if using subclass 1, exactly four multiframes must be used. after the last /a/ character of the last ilas, the multiframe data begins streaming. the receiver adjusts the position of the /a/ char acter such that it aligns with the internal lmfc of the receiver at this point. step 3 : data streaming in this phase, data is streamed from the transmitter block to the receiver block. optionally, data can be scrambled. scrambling does not start until the very first octet following the ilas. the receiver block processes and monitors the data it receiv es for errors, including ? bad running disparity ( 8 - bit/ 10 - bit error) ? not in table ( 8 - bit/ 10- bit error) ? unexpected control character ? bad ilas ? interlane skew erro r (through character replacement) if any of these errors exist, they are reported back to the transmitter in one of a few ways (see the jesd204b error monitoring section for details): ? signal assertion. r esynchroniz ation ( syncoutx signal pulled low) is requested at each error for the last two errors. for the first three errors, an optional resynchronization request can be asserted when the error counter reaches a set error threshold. ? for the first three errors, each multiframe with an error in it causes a small pulse of programmable width on syncoutx . ? errors can optionally trigger an irq event, which can be sent to the transmitter. see to the jesd204b test modes section for v arious test modes for verifying the link integrity . l receive lanes (latest arrival) l aligned receive lanes 0 character elastic buffer delay of latest arrival k = k28.5 code group synchronization comma character a = k28.3 lane alignment symbol f = k28.7 frame alignment symbol r = k28.0 start of multiframe q = k28.4 start of link configuration data c = jesd204 link configuration parameters d = dx.y data symbol 4 character elastic buffer delay of earliest arrival l receive lanes (earliest arrival) k k k k k k k r d d k k k r d d d d a r q c c d d a r q c c d d a r d d d d a r d d k k k k k k k r d d d d a r q c c d d a r d d 1 1389-149
data sheet AD9154 rev. b | page 39 of 124 lane fifo the fifos in front of the crossbar switch and deframer synchronize the samples sent on the high speed serial data interface with the deframer clock by adjust ing the phase of the incoming data. the fifo absorbs timing variations between the data source and the deframer; this allows up to two pclock cycles of drift from the transmitter. the fifo_status_reg_0 register and fifo_status_reg_1 register (register 0x30 c and register 0 x 30 d, respectively) can be monitored to identify whether the fifos are full or empty. lane fifo irq an aggregate lane fifo error bit is also available as an irq event. use register 0x01f[1] to enable the fifo error bit, and then use regist er 0x023[1] to read back its status and reset the irq signal. see the interrupt request operation section for more information. crossbar switch register 0x308 to register 0x30b allow arbitrary mapping of physical lanes (serdinx ) to logical lanes used by the serdes deframers. table 39 . crossbar registers address bits logical lane 0x308 [2:0] xbarval0 0 x 308 [5:3] xbarval 1 0x309 [2:0] xbarval 2 0 x 309 [ 5:3 ] xbarval 3 0x30a [2:0] xbarval 4 0 x 30a [ 5:3 ] xbarv al 5 0 x 30b [ 2:0 ] xbarval 6 0 x 30 b [ 5:3 ] xbarval 7 write each xbarvalx with the number (x) of the desired physical lane (serdinx) fr om which to get data. by default, all logical lanes use the corresponding physical lane as their data source. for example, b y default xbarvalx = 0, so logical lane 0 gets data from physical lane 0 (serdin0). if instead the user wants to use ser din4 as the source for logical lane 0, the user must write xbarvalx = 4 . lane inversion register 0x334 allows the inversion of desired logical lanes, which can be used to ease routing of the serdinx signals. for each logical lane x, set bit x of register 0x334 to 1 to invert the lane. deframers the AD9154 consists of two quad b yte deframers (qbds). each deframer takes in the 8 - bit/10 - bit encoded data from the deserializer (via the crossbar switch), decodes it, and descrambles it into jesd204b frames before passing it to the transport layer to be converted to dac samples. the def ramer processes four symbols (or octets) per processing clock (pclock) cycle. in single link mode, deframer 0 is used exclusively and deframer 1 remains inactive. in dual link mode, both qbds are active and must be configured separately using the sel_reg_ map_1 bit (register 0x300[2]) to select the link to be configured . the duallink bit (register 0x300[3]) =1 for dual link, or 0 for single link. each deframer uses the jesd204b parameters that the user has programmed into the register map to identify how th e data has been packed and how to unpack it. the jesd204b parameters are discussed in detail in the transport layer section; many of the parameters are also needed in the transport layer to convert jesd204b frames into samples. descrambler the AD9154 provides an optional descrambler block using a self synchronous descrambler with a polynomial: 1 + x 14 + x 15 . enabling data scrambling reduces the spectral p eaks produced when the same data octets repeat from frame to frame. it also makes the spectrum data indepen dent so that possible frequency selective effects on the electri cal interface do not cause data dependent errors. descrambling of the data is enabled by setting the scr bit (register 0 x 453[ 7 ]) to 1 . syncing lmfc signals the first step in guaranteeing synchronization across links and devices begins with syncing the lmfc sig nals. each dac dual ( dac dual a = dac0/dac1 a nd dac dual b = dac2/dac3) has its o wn lmfc signal. in subclass 0, the lmfc signals for each of the two links are synchronized to an internal processing clock. in subclass 1 , all lmfc signals (for all duals and devices) are synchronized to an external sysref signal. sysref signal the sysre f signal is a differential source synchronous input that synchronizes the lmfc signals in both the transmitter and receiver in a jesd 204 b subclass 1 system to achieve deterministic latency. the sysref signal is an active high signal sampled by the device clock rising edge. it is best practice that the device cloc k and the sysref signals be generated by the same source, such as a de vice from the ad9516 - 0 , ad9516 - 1 , ad9516 - 2 , ad9516 - 3 , ad9516 - 4 , and ad9516 - 5 family of c lock generator s, so that the phase alignment between the signals is fixed. when designing for optimum deterministic latency operation, consider the timing distribution skew of the sysref signal in a multipoint link system (multichip). the AD9154 supports a single pulse or step, or a periodic sysref signal. the periodicity can be continuous, strobed, or gapped periodic.
AD9154 data sheet rev. b | page 40 of 124 to avoid this common - mode current draw, use a 50% duty - cycle periodic sysref signal with ac coupling capacitors. if ac - coupled, the ac coupling capacitors combine with the resistors shown in figure 50 to create a high - pass filter with an rc time constant of = rc. select c such that > 4/sysref frequency . in addition, the edge rate must be sufficiently fast at least 1.3 v/ns is recommended per table 5 . figure 50 . sysref input circuit lm fc synchronization modes overview the AD9154 supports various lmfc sync processing modes. these modes are one - shot , continuous, windowed continuous, and monitor modes. all sync processing modes pe rform a phase check to see that the lmfc is phase aligned to an alignment edge. in subclass 1, the sysref pulse acts as the alignment edge; in subclass 0, an internal processing clock acts as the alignment edge. if the signals are not in phase, a clock ro tation occu rs to align the signals. the sync modes are described in the following sections . see the lmfc sync hronization procedure section for details on the procedure for syncing the lmfc signals. one - shot sync mo de (syncmode = 0 x1 ) in one - shot sync mode, a phase check occurs on only the first alignment edge received after the sync machine is armed. if the pha se error is larger than a specified window error tolerance , a phase adjustment occurs. though an lmfc synch ronization occurs only once, the sysref signal can still be continuous. continuous sync mode (syncmode = 0 x2 ) continuous mode must only be used in subclass 1 with a periodic sysref signal. in continuous mode, a phase check/alignment occurs on every align ment edge. c ontinuous mode differs from the one - shot mode in two ways. first, no spi cycle is required to arm the device; the alignment edge seen after continuous mode is enabled results in a phase check. second, a phase check (and when necessary, clock r otation) occurs on every alignment edge in continuous mode. the one caveat to the previous statement is that when a phase rotation cycle is underway, subsequent alignment edges are ignored until the logic lane is ready again. the maximum acceptable phase e rror (in dac clock cycles) between the alignment edge and the lmfc edge is set in the error window tolerance register. if continuo us sync mode is used with a non zero error window tolerance, then a phase check occurs on every sysref pulse, but an alignment occurs only if the phase error is greater than the specified error window tolerance. if the jitter of the sysref signal violates the setup and hold time specification s given in table 5 , and therefore causes phase error uncertainty, the error tolerance can be increased to avoid constant clock rotations. note that this means that the latency is less deterministic by the size of the window. if the error window tolerance must be set above 3, subclass 0 with a one - shot sync is recommended . for debug pu rposes, syncarm (register 0x03a, bit 6 ) inform s the user that alignment edges are being received in continuous mode. because the syncarm bit is self cleared after an alignment edge is received, the user can arm th e sync ( syncarm (register 0x03a, bit 6 ) = 1), and then read back syncarm. if syncarm = 0, the alignment edges are being received and phase checks are occurring. arming the sync machine in this mode does not affect the operation of the device. one - shot then monitor sync mode (syncmode = 0 x9 ) in one - shot then monitor mode, the user can monitor the phase error in real time. use this sync mode with a periodic sysref signal. a phase check and alignment occurs on the first alignment edge received after the sync machine is armed. on all subsequent alignment edges , the phase is monitored and reported, but no clock phase adjustment occurs. the phase error can be monitored on the currerr_l register, (register 0x03c , bits [7 :0]). immediately after an alignment occurs, currerr x = 0 to indicate that there is no difference between the alignment edge and the lmfc edge. on every subsequent alignment edge, the phase is checked. if the alignment is lost, the phase error is reported in the currerr_l register in dac clock cycles . if the phase error is beyond the selected wi ndow tolerance (register 0x034 , bits [2:0]), one bit of register 0x03d , bits [7:6] is set high , depending on whether the phase error is on low or high side. when an alignment occurs, snapshots of the last phase error (re gister 0x03c , bits [3:0]) and the corresponding error flags (register 0x03d , bit 7 and bit 6 ]) are placed into readable registers for reference (register 0 x 038 and register 0 x 039, respectively). lmfc sync hronization procedure the procedure for enabling the lmfc sync is as follows: 1. set register 0x008 to 0x03 to sync the lmfc for both dac duals (dac 0 /dac 1 and dac 2 /dac 3 ) 2. set the desired sync processing mode. the sync processing mode settings are listed in table 40. 3. for subclass 1, set the error window according to the uncertainty of the sysref signal relative to the dac clock and the tolerance of the application for dete rministic latency uncertainty. the s ync window tolerance settings are given in table 41. 4. enable sync by wri ting 1 to syncenable (register 0x03a, bit 7 ). 3k? ~600mv 1.2v sysref+ sysref? 3k? 1 1389-014
data sheet AD9154 rev. b | page 41 of 124 5. if in one - shot mode, arm the sync machine by writing 1 to sy ncarm (register 0x03a, bit 6 ). 6. if in subclass 1, ensure that at least one sysref pulse is sent to the device. 7. check the status by reading the following bit fields: a) ref _busy (register 0x03b , bit 7 ) = 0 to indicate that the sync logic is no longer busy. b) ref _lo ck (register 0x03b, bit 3 ) = 1 to indicate that the signals are aligned. this bit updates on every phase check. c) re f _wlim (register 0x03b, bit 1 ) = 0 to indicate that the phase error is not beyond the specified error window. this bit updates on every phase check. d) refrota (register 0x03b, bit 2 ) = 1 if the phases were not aligned before the sync and an alignment occurre d, this indicates that a clock alignment occurred. this bit is sticky and can be cleared only by writing to the syncclrstky control bit (register 0x03 a , bit 5 ). e) ref _trip (register 0x03b, bit 0 ) = 1 to indicate alignment edge received and phase check occurr ed. this bit is sticky and can be cleared only by writing to the syncclrstky control bit (register 0x03 a , bit 5 ). table 40 . sync processing modes sync processing mode syncmode (register 0x03a , bits [ 3:0 ]) one - shot 0 x 01 continuous 0 x 02 one - shot then monitor 0 x 09 table 41 . sync window tolerance sync error window tolerance errwindow (register 0x034 , bits [ 2:0 ]) 1/2 dac clock cycles 0 x 00 1 dac clock cycles 0 x 01 2 dac clock cycles 0 x 02 3 dac clock cycle s 0 x 03 lmfc sync irq the sync status bits ( ref lock, refrota , ref t r i p, a n d ref wli m) are available as irq events. use register 0x021 , bits [3:0] to enable the sync status bits for dac dual a (dac0 and dac1), and then use register 0x025 , bits [3:0] to read ba ck their statuses and reset the irq signals. use register 0x022 , bits [3:0] to enable the sync status bits for dac dual b (dac2 and dac3), and then use register 0x026 , bits [3:0] read back their statuses and reset the irq signals. deterministic latency j esd204b systems contain various clock domains distributed throughout each system. data traversing from one clock domain to a different clock domain can lead to ambiguous delays in the jesd204b link. these ambiguities lead to nonrepeatable latencies across the link from power cycle to power cycle with each new link establishment. section 6 of the jesd204b specification addresses the issue of deterministic latency with mechanisms defined as subclass 1 and subclass 2. the AD9154 supports jesd204b s ubclass 0 and subclass 1 opera tion, but not subclass 2. write the subclass to register 0x301 , bits [2:0] and once per link to register 0x458 , bits [ 7:5 ]. subclass 0 this mode does not require any signal on the sysref pins, which can be left disconnected. subclass 0 still requires that all lanes arrive within the same lmfc cycle and the dual dacs must be synchronized to each other. minor subclass 0 caveats because the AD9154 requires an ilas, the nonmultiple converter single lane (nmcda - sl) case from the jesd204a specification is only supported when using the optional ilas. error reporting using syncoutx is not supported when using sub class 0 with f = 1. subclass 1 this mode gives deterministic latency and allows links to be synced to within ? a dac clock period. it requires an external sysref signal that is accurately phase aligned to the dac clock. deterministic latency requirements several key factors are required for achieving deterministic latency in a jesd 204 b subclass 1 system. ? the sysref signal distribution skew within the system must be less than the desired uncertainty. ? the sysref setup and hold time requirements must be met for each device in the system. ? the total latency variation across all lanes, links and devices must be 10 pclock periods. this includes both variable delays and the variation in fixed delays from lane to lane, link to link, and device to device in the system.
AD9154 data sheet rev. b | page 42 of 124 link delay the link delay of a jesd204b system is the sum of fixed and variable delays from the transmitter, channel and receiver , as shown in figure 53. for proper functioning, all lanes on a link m ust be read during the same lmfc period. section 6.1 of the jesd204b specification states that the lmfc period must be larger than the maximum link delay. for the AD9154 , this is not necessarily the case; instead , the AD9154 uses a local lmfc for each link (lmfc rx ) that can be delayed from the sysref aligned lmfc. because the lmfc is periodic, this can account for any amount of fixed dela y. as a result, the lmfc period must only be larger than the variation in the link delays, and the AD9154 can achieve proper performance with a smaller total latency. figure 51 and figure 52 show a case where the link delay is larger than an lmfc period. note that it can be accommodated by delaying lmfc rx . figure 51 . link delay > lmfc p eriod example figure 52 . lmfc delay to compen sate for link delay > lmfc figure 53 . jesd204b link delay = fixed delay + variable delay ilas data power cycle variance lmfc aligned data early arriving lmfc reference late arriving lmfc reference 1 1389-151 ilas data frame clock power cycle variance lmfc aligned data lmfc rx lmfc_delay lmfc reference for all power cycles 1 1389-152 11389-153 ilas ilas fixed delay variable delay power cycle variance data lmfc aligned data at rx output data at tx input data dsp channel logic device (jesd204b tx) jesd204b rx dac link delay = delay fixed + delay variable
data sheet AD9154 rev. b | page 43 of 124 the method for setting the lmfcdel and lmfcvar is described i n the link delay setup section. setting lmfcdel appropriately ensures that all the correspondin g data samples arrive in the same lmfc period. then lmfcvar is written into the receive buffer delay (rbd) to absorb a ll link delay variation. this ensures that all data samples have arrived before reading. by setting these to fixed values across runs and devices, deterministic latency is achieved. the rbd described in the jesd204b specific ation takes values from 1 to k f rame c lock cycles, while the rbd of the AD9154 takes values from 0 pclock cycles to 10 pc l ock cycles. as a result, up to 10 pclock cycles of total delay variation can be absorbed. because lmfcvar is in pclock cycles, and lmfcdel is in f rame c lock cycles, a conversion between these two units is needed. the pclockfactor, or number of frame clock cycles per pclock cycle, is equal to 4/f. for more information on this relationship, see the clock multiplication relationships section. two examples follow that show how to determine lmfcvar and lmfcdel. after they are calculated, write lmfcdel into both register 0x304 and register 0x305 for all devices in the system , and write lmfcvar to both register 0 x 306 and register 0 x 307 for all devices in the system. link delay setup example, with known delays all the known system delays can be used to calculate lmfcvar and lmfcdel as described in the link delay setup section. the example shown in figure 54 is demonstrated in the following steps according to the procedure outlined in the link delay setup section. note th at this example is in subclass 1 to achieve deterministic latency, which has a pclockfactor (4/f) of 2 f rame c lock cycles per pclock cycle , and uses k = 32 (frames per multiframe). b ecause pcbfixed < pclockperiod, pcbfixed is negligible in this example and is not included in the calculations. 1. find the receiver delays using table 8 . rxfixed = 17 pclock cycles rxvar = 2 pclock cycles 2. find the transmitter delays. the equivalent table in the example jesd 204b core (imp lemented on a gth or gtx transceiver on a virtex - 6 fpga) states that the delay is 56 2 byte clock cycles. because the pclockrate = byterate/4 as described in the clock multiplication relationships section, the t ransmitter delays in pclock cycles are: txfixed = 54/4 = 13.5 pclock cycles txvar = 4/4 = 1 pclock cycle 3. calculate mindelaylane as follows: mindelaylane = floor ( rxfixed + txfixed + pcbfixed ) = floor ( 17 + 13.5 + 0 ) = floor ( 30.5 ) mindelaylane = 30 4. calcul ate fall_count_d elaylane as follows: fall_count_d elaylane = ceil ing ( rxfixed + rx var + txfixed + txvar + pcbfixed )) = ceiling( 17 + 2 + 13.5 + 1 + 0 ) = ceiling( 33.5 ) fall_count_d elaylane = 34 5. calculate lmfcvar as follows: lmf cvar = ( fall_count_d elaylane + 1) ? ( mindelay ? 1 ) = ( 34 + 1 ) ? ( 30 ? 1 ) = 35 ? 29 lmfcvar = 6 pclock cycles 6. calculate lmfcdel as follows: lmfcdel = (( mindelay ? 1) pclockfactor ) % k = (( 30 ? 1 ) 2 ) % 32 = ( 29 2 ) % 32 = 58 % 32 lmfcdel = 26 frame c lock cycles 7. write lmfcdel to both register 0x304 and register 0x305 for all devices in the system. write lmfcvar to both register 0x306 and register 0x307 for all devices in the system. figure 54 . lmfc_delay calculation example 11389-154 frame clock lmfc pclock data data at tx framer ilas lmfc rx total fixed latency = 30 pclock cycles lmfc delay = 26 frame clock cycles pcb fixed delay data aligned lane data at rx deframer output ilas total variable latency = 4 pclock cycles tx var delay rx var delay
AD9154 data sheet rev. b | page 44 of 124 link delay setup example, with out known delay if the system delays are not known, the AD9154 can read back the link latency between lmfc rx for each link and the sysref aligned lmfc. this information is used to calculate lmfcva r and lmfcdel, as shown in the without known delays section. figure 56 shows how dyn_link_latency_x (register 0x302 and register 0x303) provides a readback showing the dela y (in pclock cycles) between lmfc rx and the transition from ilas to the first data sample. by repeatedly power - cycling and taking this measurement, the minimum and maximum delays across power cycles can be determined and used to calculate lmfcvar and lmfcd el. the example shown in figure 56 is demonstrated in the following steps according to the procedure outlined in the without known delays section. note that this example is in subclass 1 to achieve deterministic latency, which has a pclockfactor ( frameclockrate / pclkrate ) of 2 and uses k = 16 ; therefore pclockspermf = 8 . 1. in figure 56 , for link a, link b, and link c, the system contai ning the AD9154 (including the transmitter) is power cycled and configured 20 times. the AD9154 is configured as described in the device setup guide section. as the point of this exercise is to determine lmfcdel and lmfcvar, the lmfcdel is programmed to 0 and the dyn_ link_latency_x is read from register 0x302 and register 0x303 for link 0 and link 1, respectively . the variation in the link latency over the 20 runs is shown in figure 56 in gray . ? link a gives readbacks of 6, 7, 0, and 1. note that the set of recorded delay values rolls over the edge of a multiframe at the bo undary k /pclockfactor = 8. add pclockspermf = 8 to low set. delay values range from 6 to 9 . ? link b gives delay values from 5 to 7 . ? link c gives delay values from 4 to 7 . 2. calculate the minimum of all delay measurements across all power cycles, links, and de vices: mindelay = min(all delay values) = 4 3. calculate the maximum of all delay measurements across all power cycles, links, and devices: fall_count_d elay = max(all delay values) = 9 4. calculate the total delay variation (with guard band) across all power cyc les, links, and devices: lmfcvar = ( fall_count_d elay + 1) ? ( mindelay ? 1 ) = (9 + 1) ? (4 ? 1) = 10 ? 3 = 7 pclock cycles 5. calculate the minimum delay in f rame c lock cycles (with guard band) across all power cycles, links, and devices: lmfcdel = (( mindelay ? 1) pclockfactor ) % k = ((4 ? 1) 2) % 16 = (3 2 ) % 16 = 6 % 16 = 6 frame c lock cycles 6. write lmfcdel to both register and register 0x305 for all devices in the system. write lmfcvar to both register 0x306 and register 0 x 307 for all devices in the system. figure 55 . dyn_l ink_latency illustration figure 56 . multilink synchronization settings, derived method example ilas data sysref aligned data lmfc rx dyn_link_latency 1 1389-155 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 dyn_link_latency_cnt aligned data (link a) deterministically delayed data lmfc rx aligned data (link b) aligned data (link c) frame clock lmfc pclock data ilas data ilas data ilas data ilas lmfc_delay = 6 (frame clock cycles) lmfcvarx = 7 (pclock cycles) 11389-156
data sheet AD9154 rev. b | page 45 of 124 transport layer figure 57 . transport layer block diagram the transport layer receives the descrambled je sd204b frames and converts them to dac samples based on the programmed jesd204b parameters shown in table 42 . a number of device parameters are defined in table 43. table 42 . jesd204b transport layer parameters parameter description f number of octets per frame per lane: 1 , 2 , or 4 . k number of frames per multiframe. k = 32 if f = 1 , k = 16 or 32 otherwise. l number of lanes per converter device (per link), as follows. 1 , 2 , 4 , or 8 (single link mode). 1 , 2 , or 4 (dual link mode). m number of converters per device (per link), as follows. 1 , 2 , or 4 (single link mode). 1 or 2 (dual link mode). s number of samples per converter, per frame : 1 or 2 . table 43 . jesd204b device parameters parameter description cf number of control words per device clock per link. not supported, must be 0 . cs number of control bits per conversion sample. not supported, must be 0 . hd h igh density user data format. used when samples must be split across lanes. set to 1 when f = 1 , otherwise 0 . n converter resolution = 16. n prime ( n ? certain combinations of these parameters, called jesd204b op erating modes, are supported by the AD9154 . see table 44 and table 45 for a list of supported modes, along with their associated clock relations hips. delay buffer 1 delay buffer 0 f2s_0 f2s_1 dac 1_i0[15:0] dac 2_q0[15:0] pclk_1 lane 0 octets lane 7 octets pclk_0 spi control lane 3 octets lane 4 octets dac 3_i0[15:0] dac 4_q0[15:0] transport layer (qbd) spi control 1 1389-157
AD9154 data sheet rev. b | page 46 of 124 table 44 . single link jesd204b operating modes mode parameter 0 1 2 3 4 5 6 7 9 10 m (converter count) 4 4 4 4 2 2 2 2 1 1 l (lane count) 8 8 4 2 4 4 2 1 2 1 s (samples per converter per frame) 1 2 1 1 1 2 1 1 1 1 f (o ctets per frame, per lane) 1 2 2 4 1 2 2 4 1 2 k 1 (frames per multiframe) 32 16/32 16/32 16/32 32 16/32 16/32 16/32 32 16/ 32 hd (high density) 1 0 0 0 1 0 0 0 1 0 n (converter resolution) 16 16 16 16 16 16 16 16 16 16 np (bits per sample) 16 16 16 16 1 6 16 16 16 16 16 example clocks for 10 gbps lane rate pclock rate (mhz) 250 250 250 250 250 250 250 250 250 250 frame clock rate (mhz) 1000 500 500 250 1000 500 500 250 1000 500 data rate (mhz) 1000 1000 500 250 1000 1000 500 250 1000 500 1 k must be 32 in mode 0, mode 4, and mode 9. k can be 16 or 32 in all other modes. table 45 . dual link jesd204b operating modes for link 0 and link 1 mode parameter 4 5 6 7 9 10 m (converter count) 2 2 2 2 1 1 l (lane count) 4 4 2 1 2 1 s (samples per converter per frame) 1 2 1 1 1 1 f (octets per frame per lane) 1 2 2 4 1 2 k 1 (frames per multiframe) 32 16/32 16/32 16/32 32 16/32 hd (high density) 1 0 0 0 1 0 n (converter resolution) 16 16 16 16 16 16 np (bits per sample) 16 16 16 16 16 16 example clocks for 10 gbps lane rate pclock rate (mhz) 250 250 250 250 250 250 frame clock rate (mhz) 1000 500 500 250 1000 500 data rate (mhz) 1000 1000 500 250 1000 500 1 k must be 32 in mode 4 and mode 9. k can be 16 or 32 in all other modes.
data sheet AD9154 rev. b | page 47 of 124 configuration parameters the AD9154 modes refer to the link configuration parameters for l , k , m , n , np , s , and f . table 46 provides the description and addresses for these settings. table 46 . configuration parameters jesd 204 b setting description address [bits] l ? 1 number of lanes ? 1 . 0 x 453 [ 4:0 ] f 1 ? 1 number of ((octets per frame) per lane) ? 1 . 0 x 454 [ 7:0 ] k ? 1 n umber of frames per multiframe ? 1. 0 x 455 [ 4:0 ] m ? 1 number of converters ? 1 . 0 x 456 [ 7:0 ] n ? 1 converter bit resolution ? 1 . 0 x 457 [ 4:0 ] n p ? 1 bit packing per sample ? 1 . 0 x 458 [ 4:0 ] s ? 1 number of ((samples per converter) per frame) ? 1 . 0 x 459 [ 4:0 ] hd high density format. set to 1 if f = 1 . leave at 0 if f 1 . 0 x 45a[ 7 ] f 1 f parameter, in ((octets per frame) per lane). 0 x 476 [ 7:0 ] did device id. match the device id sent by the transmitter. 0 x 450 [ 7:0 ] bid bank id. match the bank id sent by the transmitter. 0 x 451 [ 3:0 ] lid 0 lane id for l ane 0. match the lane id sent by the transmitter on logical lane 0 . 0 x 452 [ 4:0 ] jesdv er jesd version . match the version sent by the transmitter ( 0 x 0 = jesd 204 a, 0 x 1 = jesd 204 b). 0 x 459 [ 7:5 ] 1 f must be programmed in two places : register 0x454 , bits [7:0] and register 0x459 , bits [7:0] . data flow through the jesd204b receiver the link configurat ion parameters determine how the serial bits on the jesd204b receiver interface are deframed and passed on to the dacs as data samples. figure 58 shows a detailed flow of the data through the various hardware block s for mode 4 ( l = 4, m = 2, s = 1, f = 1). simplified flow diagrams for all other modes are provided i n figure 59 th rough figure 67. single and dual link configuration the AD9154 uses the settings contained in table 44 and table 45. mode 0 to mode 10 can be used for single link opera tion. mode 4 to mode 10 can also be used for dual link operation. to use dual link mode, set duallink (register 0x300 , bit 3 ) to 1. in dual link mode, link 1 must be programmed with identical parameters to link 0. to write to link 1, set sel_reg_map_1 (reg ister 0x300, bit 2 ) to 1 . if single link mode is being used, a small amount of power can be saved by powering down the output buffer for syncout1 , which can be done by setting register 0x203, bit 0 = 1 . checking proper configuration as a convenience, the AD9154 provides some quick configuration checks. register 0x030, bit 5 is high if an illegal lmf cdelx is used. register 0x030, bit 3 is high if an unsupported combination of l, m, f, or s is used. register 0x030, bit 2 is high if an illegal k is used. register 0x 030, bit 1 is high if an illegal subclassv is used. deskewing and enabling logical lanes after proper configuration, the logical lanes must be deskewed and enabled to cap ture data. set bit x in register 0x46c to 1 to deskew logical lane x and to 0 if that logical lane is not being us ed. then, set bit x in register 0x47d to 1 to enable logical lane x and to 0 if that logical lane is not being used.
AD9154 data sheet rev. b | page 48 of 124 figure 58 . jesd204b mode 4 data deframing data link layer transport layer physical layer deserializer converter 0, sample 0 d15 dac0 dac1 nibble group 0 nibble group 1 deserializer deserializer serial jesd204b data (l = 4) samples split across lanes (hd = 1) 40 bits parallel data (encoded and scrambled) 1 octet per lane (f = 1) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) 2 converters (m = 2) serdin3 serdin2 j9 j8 j1 j0 j19 j18 j11 j10 lane 0, octet 0 lane 1, octet 0 lane 2, octet 0 lane 3, octet 0 converter 1, sample 0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s15 s14 s13 s12 s19 s18 s17 s16 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 s15 s14 s13 s12 s19 s18 s17 s16 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 descrambler 10-bit/8-bit decode serdin1 serdin0 j9 j8 j1 j0 j19 j18 j11 j10 1 1389-158 deserializer
data sheet AD9154 rev. b | page 49 of 124 mode configuration maps table 47 through table 56 contain the spi configuration maps for each mode shown in figure 59 through figure 67. figure 59 through figure 67 show the associated data flow through the deframing process of the jesd204b receiver for each of the modes. mode 0 to mode 10 apply to single link operation. mode 4 to mode 10 also apply to dual link operation. register 0x300 must be set accordingly for single or dual link operation. additional details regarding all the spi registers can be found in the register summary and register details sections. table 47. spi configuration mapregister se ttings for jesd204b parameters for mode 0 address setting description 0x453 0x07 or 0x87 register 0x453, bit 7 = 0 or 1: scrambling disabled or enabled; register 0x453[4:0] = 0x7: l = 8 lanes per l ink 0x454 0x00 register 0x454, bits[7:0] = 0x00: f = 1 octet per frame 0x455 0x1f register 0x455, bits[4:0] = 0x1f: k = 32 frames per multiframe 0x456 0x03 register 0x456, bits[7:0] = 0x03: m = 4 converters per link 0x457 0x0f register 0x457, bits[7:6] = 0x0: always set cs = 0; register 0x457, bits[4:0] = 0xf: n = 16, always set to 16-bit resolution 0x458 0x0f or 0x2f register 0x458, bits[7:5] = 0x0 or 0x1: subclass 0 or subclass 1; register 0x458, bits[4:0] = 0xf: np = 16 b its per sample 0x459 0x20 register 0x459, bits[7:5] = 0x1: jesd204b version; register 0x459, bits[4:0] = 0x0: s = 1 sample per converter per frame 0x45a 0x80 register 0x45a, bit 7 = 1: hd = 1; regi ster 0x45a, bits[4:0] = 0x00: always set cf = 0 0x46c 0xff register 0x46c, bits[7:0] = 0xff: deskew link lane 0 to link lane 7 0x476 0x01 register 0x476, bits[7:0] = 0x01: f = 1 octet per frame 0x47d 0xff register 0x47d, bits[7:0] = 0xff : enable link lane 0 to link lane 7 figure 59. jesd204b mode 0 data deframing j19 j18 j11 j10 j9 j8 j1 j0 j9 j8 j1 j0 j19 j18 j11 j10 1 octet per lane (f = 1) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) dac0 dac1 dac2 dac3 serial jesd204b data (l = 8) samples split across lanes (hd = 1) nibble group 0 serdin0 serdin1 serdin2 serdin3 j19 j18 j11 j10 j9 j8 j1 j0 serdin2 serdin3 j19 j18 j11 j10 j9 j8 j1 j0 serdin6 serdin7 converter 0, sample 0 d15 ... d0 lane 0, octet 0 lane 1, octet 0 nibble group 1 converter 1, sample 0 d15 ... d0 lane 2, octet 0 lane 3, octet 0 nibble group 2 converter 2, sample 0 d15 ... d0 lane 4, octet 0 lane 5, octet 0 nibble group 3 converter 3, sample 0 d15 ... d0 lane 6, octet 0 lane 7, octet 0 4 converters (m = 4) 11389-159
AD9154 data sheet rev. b | page 50 of 124 table 48 . spi conf iguration map register settings for jesd204b parameters for mode 1 address setting description 0 x 453 0 x 07 or 0 x 87 register 0x453 , bit 7 = 0 or 1: scrambling disabled or enabled; register 0x453 , bits [4:0] = 0x7: l = 8 lanes per link 0 x 454 0 x 01 register 0x 454, bits [ 7:0 ] = 0 x 01 : f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455 , bits [4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x03 register 0x456 , bits [7:0] = 0x03: m = 4 converters per link 0x457 0x0f register 0x457 , bits [7:6] = 0 x0: always set cs = 0; register 0x457 , bits [4:0] = 0x0f: n = 16, always set to 16 - bit resolution 0x458 0x0f or 0x2f register 0x458 , bits [7:5] = 0x0 or 0x1: subclass 0 or subclass 1, register 0x458 , bits [4:0] = 0xf: np = 16 bits per sample 0x459 0x21 regi ster 0x459 , bits [7:5] = 0x1: set to jesd204b version, register 0x459 , bits [4:0] = 0x1: s = 2 samples per converter per frame 0 x 45a 0 x 00 register 0x45a , bit 7 = 0: hd = 0; register 0x45a , bits [ 4:0 ] = 0 x 00 : always set cf = 0 0x46c 0xff register 0x46c , bits [7:0] = 0xff: deskew link lane 0 to link lane 7 0x476 0x02 register 0x476, bits [7:0] = 0x02: f = 2 octets per frame 0x47d 0xff register 0x47d , bits [7:0] = 0xff: 8 lanes enabled, set one bit per lane to enable figure 60 . jes d204b mode 1 data deframing j19 j18 j1 j0 j19 j18 j1 j0 j19 j18 j1 j0 j19 j18 j1 j0 2 octets per lane (f = 2) 16-bit nibble group (n = 16) 2 samples per converter per frame (s = 2) dac0 dac1 dac2 dac3 serial jesd204b data (l = 8) samples not split across lanes (hd = 0) nibble group 0 nibble group 1 serdin0 serdin1 serdin2 serdin3 j19 j18 j1 j0 j19 j18 j1 j0 serdin2 serdin3 j19 j18 j1 j0 j19 j18 j1 j0 serdin6 serdin7 conv 0, smpl 0 conv 0, smpl 1 d15 ... d0 (0) d15 ... d0 (1) l 0, o 0 l 0, o 1 l 1, o 0 l 1, o 1 4 converters (m = 4) nibble group 2 nibble group 3 conv 1, smpl 0 conv 1, smpl 1 d15 ... d0 (0) d15 ... d0 (1) l 2, o 0 l 2, o 1 l 3, o 0 l 3, o 1 nibble group 4 nibble group 5 conv 2, smpl 0 conv 2, smpl 1 d15 ... d0 (0) d15 ... d0 (1) l 4, o 0 l 4, o 1 l 5, o 0 l 5, o 1 nibble group 6 nibble group 7 conv 3, smpl 0 conv 3, smpl 1 d15 ... d0 (0) d15 ... d0 (1) l 6, o 0 l 6, o 1 l 7, o 0 l 7, o 1 1 1389-160
data sheet AD9154 rev. b | page 51 of 124 table 49 . spi configuration map register settings for jesd204b parameters for mode 2 address setting description 0x453 0x03 or 0x83 register 0x453 , bit 7 = 0 or 1: scrambling disabled or e nabled; register 0x453 , bits [4:0] = 0x3: l = 4 lanes per link 0 x 454 0 x 01 register 0x454 , bits [ 7:0 ] = 0 x 01 : f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455 , bits [4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x03 register 0x456 , bits [7:0] = 0x03: m = 4 converters per link 0x457 0x0f register 0x457 , bits [7:6] = 0x0: always set cs = 0; register 0x457 , bits [4:0] = 0x0f: n = 16, always set to 16 - bit resolution 0x458 0x0f or 0x2f register 0x458 , b its [7:5] = 0x0 or 0x1: subclass 0 or subclass 1, register 0x458 , bits [4:0] = 0xf: np = 16 bits per sample 0x459 0x20 register 0x459 , bits [7:5] = 0x1: set to jesd204b version, register 0x459 , bits [4:0] = 0x0: s = 1 sample per converter per frame 0 x 45a 0 x 00 register 0x45a , bit 7 = 0: hd = 0; register 0x45a , bits [ 4:0 ] = 0 x 00 : always set cf = 0 0x46c 0x 0 f register 0x46c , bits [7:0] = 0xff: deskew link lane 0 to link lane 3 0x476 0x02 register 0x476, bits [7:0] = 0x02: f = 2 octets per frame 0x47d 0x0f register 0x47d , bits [7:0] = 0x0f: e nable li nk lane 0 to link lane 3 figure 61 . jesd204b mode 2 data deframing j19 j18 j1 j0 j19 j18 j1 j0 serdin0 serdin1 j19 j18 j1 j0 serdin2 j19 j18 j1 j0 serdin3 2 octets per lane (f = 2) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) dac0 dac1 dac2 dac3 serial jesd204b data (l = 4) samples not split across lanes (hd = 0) nibble group 0 converter 0, sample 0 nibble group 0 d15 ... d0 (0) lane 0, octet 0 lane 0, octet 1 nibble group 1 converter 1, sample 0 d15 ... d0 (0) lane 1, octet 0 lane 1, octet 1 nibble group 2 converter 2, sample 0 d15 ... d0 (0) lane 2, octet 0 lane 2, octet 1 nibble group 3 converter 3, sample 0 d15 ... d0 (0) lane 3, octet 0 lane 3, octet 1 4 converters (m = 4) nibble group 1 nibble group 2 nibble group 3 1 1389-161
AD9154 data sheet rev. b | page 52 of 124 table 50 . spi configuration map register settings for jesd204b parameters for mode 3 address setting description 0x453 0x01 or 0x81 r egister 0x453, bit 7 = 0 or 1: scrambling disabled or enabled; register 0x453 , bits [4:0] = 0x1: l = 2 lanes per link 0 x 454 0 x 03 register 0x454 , bits [ 7:0 ] = 0 x 03 : f = 4 octets per frame 0x455 0x0f or 0x1f register 0x455 , bits [4:0] = 0x0f or 0x1f: k = 16 o r 32 frames per multiframe 0x456 0x03 register 0x456 , bits [7:0] = 0x03: m = 4 converters per link 0x457 0x0f register 0x457 , bits [7:6] = 0x0: always set cs = 0; register 0x457 , bits [4:0] = 0x0f: n = 16, always set to 16 - bit resolution 0x458 0x0f or 0x2f register 0x458 , bits [7:5] =0x0 or 0x1: subclass 0 or subclass 1, register 0x458 , bits [4:0] = 0xf: np = 16 bits per sample 0x459 0x20 register 0x459 , bits [7:5] = 0x1: set to jesd204b version, register 0x459 , bits [4:0] = 0x0: s = 1 sample per converter per frame 0 x 45a 0 x 00 register 0x45a , bit 7 = 0: hd = 0; register 0x45a , bits [ 4:0 ] = 0 x 00 : always set cf = 0 0x46c 0x 03 register 0x46c , bits [7:0] = 0xff: d eskew link lane 0 and link lane 1 0x476 0x04 register 0x476, bits[7:0] = 0x04: f = 4 octets per frame 0x47d 0x03 register 0x47d , bits [7:0] = 0x03: e nable link lane 0 and link lane 1 figure 62 . jesd204b mode 3 data deframing table 51 . spi configuration map register settings for jesd204b parameters for mode 4 address setting description 0x453 0x03 or 0x83 register 0x453 , bit 7 = 0 or 1: scrambling disabled or enabled; register 0x453 , bits [4:0] = 0x3: l = 4 lanes per link 0 x 454 0x0 0 register 0x454 , bits [ 7:0 ] = 0 x 00 : f = 1 octet per frame 0x455 0x0f or 0x1f register 0x455 , bits [4:0] = 0x0f or 0x1f: k =16 or 32 frames per multiframe 0x456 0x01 register 0x456 , bits [7:0] = 0x01: m = 2 converters per link 0x457 0x0f register 0x457 , bits [7:6] = 0x0: always set cs = 0; register 0x457 , bits [4:0] = 0x0f: n = 1 6, always set to 16 - bit resolution 0x458 0x0f or 0x2f register 0x458 , bits [7:5] = 0x0 or 0x1: subclass 0 or subclass 1, register 0x458 , bits [4:0] = 0xf: np = 16 bits per sample 0x459 0x20 register 0x459 , bits [7:5] = 0x1: set to jesd204b version, register 0x459 , bits [4:0] = 0x0: s = 1 sample per converter per frame 0 x 45a 0 x 01 register 0x45a, bit 7 = 1: hd = 1; register 0x45a , bits [ 4:0 ] = 0 x 00 : always set cf = 0 0x46c 0x0f register 0x46c , bits [7:0] = 0xff: d eskew link lane 0 to link lane 3 0x476 0x01 reg ister 0x476 , bits [7:0] = 0x01: f = 1 octet per frame 0 x 47d 0 x 0 f register 0x47d , bits [7:0] = 0x0f: enable link lane 0 to link lane 3 j19 j18 j1 j0 j39 j38 j21 j20 4 octets per lane (f = 4) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) dac0 dac1 dac2 dac3 serial jesd204b data (l = 2) samples not split across lanes (hd = 0) nibble group 0 serdin0 j39 j38 j21 j20 serdin1 j19 j18 j1 j0 converter 0, sample 0 nibble group 0 d15 ... d0 (0) lane 0, octet 0 lane 0, octet 1 nibble group 1 converter 1, sample 0 d15 ... d0 (0) lane 0, octet 2 lane 0, octet 3 nibble group 2 converter 2, sample 0 d15 ... d0 (0) lane 1, octet 0 lane 1, octet 1 nibble group 3 converter 3, sample 0 d15 ... d0 (0) lane 1, octet 2 lane 1, octet 3 4 converters (m = 4) nibble group 1 nibble group 2 nibble group 3 11389-162
data sheet AD9154 rev. b | page 53 of 124 see figure 58 for an illustration of the AD9154 jesd 204 b mode 4 data deframing process. table 52 . spi configuration map register settings for jesd204b parameters for mode 5 address setting description 0x453 0x03 or 0x83 register 0x453, bit 7 = 0 or 1: scrambling dis abled or enabled; register 0x453 , bits [4:0] = 0x3: l = 4 lanes per link 0 x 454 0 x 01 register 0x454 , bits [ 7:0 ] = 0 x 01 : f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455 , bits [4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x01 regist er 0x456 , bits [7:0] = 0x01: m = 2 converters per link 0x457 0x0f register 0x457 , bits [7:6] = 0x0: always set cs = 0; register 0x457 , bits [4:0] = 0x0f: n = 16, always set to 16 - bit resolution 0x458 0x0f or 0x2f register 0x458 , bits [7:5] = 0x0 or 0x1: subc lass 0 or subclass 1, register 0x458 , bits [4:0] = 0xf: np = 16 bits per sample 0x459 0x21 register 0x459 , bits [7:5] = 0x1: set to jesd204b version, register 0x459 , bits [4:0] = 0x1: s = 2 samples per converter per frame 0 x 45a 0 x 00 register 0x45a, bit 7 = 0: hd = 0; register 0x45a , bits [ 4:0 ] = 0 x 00 : always set cf = 0 0x46c 0x 0 f register 0x46c , bits [7:0] = 0xff: d eskew link lane 0 to link lane 3 0x476 0x02 register 0x476, bits [7:0] = 0x02: f = 2 octets per frame 0x47d 0x0f register 0x47d , bits [7:0] = 0x0 f: enable link lane 0 to link lane 3 figure 63 . jesd204b mode 5 data deframing 2 octets per lane (f = 2) 16-bit nibble group (n = 16) 2 samples per converter per frame (s = 2) dac0 dac1 serial jesd204b data (l = 4) samples not split across lanes (hd = 0) nibble group 0 converter 0, sample 0 nibble group 0 d15 ... d0 (0) lane 0, octet 0 lane 0, octet 1 nibble group 1 converter 0, sample 1 d15 ... d0 (1) lane 1, octet 0 lane 1, octet 1 nibble group 2 converter 1, sample 0 d15 ... d0 (0) lane 2, octet 0 lane 2, octet 1 nibble group 3 converter 1, sample 1 d15 ... d0 (1) lane 3, octet 0 lane 3, octet 1 2 converters (m = 2) nibble group 1 nibble group 2 nibble group 3 11389-163 j19 j18 j1 j0 j19 j18 j1 j0 serdin0 serdin1 j19 j18 j1 j0 serdin2 j19 j18 j1 j0 serdin3
AD9154 data sheet rev. b | page 54 of 124 table 53 . spi configuration map register settings for jesd204b parameters for mode 6 address setting description 0x453 0x0 1 or 0x81 register 0x453 , bit 7 = 0 or 1: scrambling disabled or enabled, register 0x453 , bits [4:0] = 0x1: l = 2 lanes per link 0 x 454 0 x 01 register 0x454 , bits [ 7:0 ] = 0 x 01 : f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455 , bits [4:0] = 0x0f or 0x1 f: k = 16 or 32 frames per multiframe 0x456 0x01 register 0x456 , bits [7:0] = 0x01: m = 2 converters per link 0x457 0x0f register 0x457 , bits [7:6] = 0x0: always set cs = 0; register 0x457 , bits [4:0] = 0x0f: n = 16, always set to 16 - bit resolution 0x458 0 x0f or 0x2f register 0x458 , bits [7:5] = 0x0 or 0x1: subclass 0 or subclass 1, register 0x458 , bits [4:0] = 0xf: np = 16 bits per sample 0x459 0x20 register 0x459 , bits [7:5] = 0x1: set to jesd204b version, register 0x459 , bits [4:0] = 0x0: s = 1 sample per f rame 0 x 45a 0 x 00 register 0x45a, bit 7 = 0: hd = 0; register 0x45a , bits [ 4:0 ] = 0 x 00 : always set cf = 0 0x46c 0x 03 register 0x46c , bits [7:0] = 0xff: d eskew link lane 0 and link lane 1 0x476 0x02 register 0x476, bits [7:0] = 0x02: f = 2 octets per frame 0x47d 0x03 register 0x47d , bits [7:0] = 0x03: enable link lane 0 and link lane 1 figure 64 . jesd204b mode 6 data deframing 2 octets per lane (f = 2) 16-bit nibble group (n = 16) 1 sample per converter per frame (s = 1) dac0 dac1 serial jesd204b data (l = 2) samples not split across lanes (hd = 0) nibble group 1 converter 1, sample 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lane 1, octet 0 lane 1, octet 1 2 converters (m = 2) j19 j18 j1 j0 j19 j18 j1 j0 serdin0 serdin1 nibble group 0 converter 0, sample 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lane 0, octet 0 lane 0, octet 1 1 1389-164
data sheet AD9154 rev. b | page 55 of 124 table 54 . spi configuration map register settings for jesd204b parameters for m ode 7 address setting description 0x453 0x00 or 0x80 register 0x453 , bit 7 = 0 or 1: scrambling disabled or enabled, register 0x453 , bits [4:0] = 0x0: l = 1 lane per link 0 x 454 0 x 03 register 0x454 , bits [ 7:0 ] = 0 x 03 : f = 4 octets per frame 0x455 0x0f or 0 x1f register 0x455 , bits [4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x01 register 0x456 , bits [7:0] = 0x01: m = 2 converters per link 0x457 0x0f register 0x457 , bits [7:6] = 0x0: always set cs = 0; register 0x457 , bits [4:0] = 0x0f: n = 1 6, always set to 16 - bit resolution 0x458 0x0f or 0x2f register 0x458 , bits [7:5] = 0x0 or 0x1: subclass 0 or subclass 1, register 0x458 , bits [4:0] = 0xf: np = 16 bits per sample 0x459 0x20 register 0x459 , bits [7:5] = 0x1: set to jesd204b version, register 0x459 , bits [4:0] = 0x0: s = 1 sample per converter per frame 0 x 45 a 0 x 00 register 0x45a, bit 7 = 0: hd = 0; register 0x45a , bits [ 4:0 ] = 0 x 00 : always set cf = 0 0x46c 0x01 register 0x46c , bits [7:0] = 0xff: deskew link lane 0 0x476 0x04 register 0x476, b its [7:0] = 0x04: f = 4 octets per frame 0x47d 0x01 register 0x47d , bits [7:0] = 0x01: enable link lane 0 figure 65 . jesd204b mode 7 data deframing 4 octets per lane (f = 4) 16-bit nibble group (n = 16) 1 sample per dac0 dac1 serial jesd204b data (l = 1) samples not split across lanes (hd = 0) nibble group 0 converter 0, sample 0 nibble group 0 d15 ... d0 lane 0, octet 0 lane 0, octet 1 nibble group 2 converter 1, sample 0 d15 ... d0 lane 0, octet 2 lane 0, octet 3 2 converters (m = 2) nibble group 1 j19 j18 j1 j0 j39 j38 j21 j20 serdin0 1 1389-165 converter per frame (s = 1)
AD9154 data sheet rev. b | page 56 of 124 table 55 . spi configuration map register settings for jesd204b parameters for mode 9 address setting description 0x453 0x01 or 0x81 register 0x453, bit 7 = 0 or 1: scrambling disabled or enabled, register 0x453 , bits [4:0] = 0x1: l = 2 lanes per link 0 x 454 0 x 00 register 0x454 , bits [7:0] = 0x00: f = 1 octet per frame 0x455 0x1f register 0x455 , bits [4:0] = 0x1f: k = 32 frames per multiframe 0x456 0x00 register 0x456 , bits [7:0] = 0x00: m = 1 converter per link 0x457 0x0f register 0x457 , bits [7:6] = 0x0: always set cs = 0; register 0x457 , bits [4:0] = 0x0f: n = 16, always set to 16 - bit resolution 0x458 0x0f or 0x2f register 0x458 , bits [7:5] = 0x0 or 0x1: subclass 0 or subclass 1, register 0x458 , bits [4:0] = 0xf: np = 16 bits per sample 0x459 0x20 register 0x459 , bits [7:5] = 0x1: set to jesd204b version, regis ter 0x459 , bits [4:0] = 0x0: s = 1 sample per converter per frame 0 x 45 a 0 x 01 regi ster 0x45a, bit 7 = 1: hd = 1; register 0x45a , bits [ 4:0 ] = 0 x 00 : always set cf = 0 0x46c 0x03 register 0x46c , bits [7:0] = 0xff: deskew link lane 0 and link lane 1 0x476 0x0 1 register 0x476, bits [7:0] = 0x01: f = 1 octet per frame 0x47d 0x03 register 0x47d , bits [7:0] = 0x03: enable link lane 0 and link lane 1 figure 66 . jesd204b mode 9 data deframing j9 j8 j1 j0 j19 j18 j11 j10 1 octet per lane 16-bit nibble group 1 sample per dac0 serial jesd204b data (l = 2) samples split across lanes (hd = 1) nibble group 0 serdin0 serdin1 converter 0, sample 0 d15 ... d0 lane 0, octet 0 lane 1, octet 0 1 converter 1 1389-166 (f = 1) (n = 16) converter per frame (s = 1) (m = 1)
data sheet AD9154 rev. b | page 57 of 124 table 56 . spi config uration map register settings for jesd204b parameters for mode 10 address setting description 0x453 0x00 or 0x80 register 0x453, bit 7 = 0 or 1: scrambling disabled or enabled, register 0x453 , bits [4:0] = 0x0: l = 1 lane per link 0 x 454 0 x 01 register 0x45 4 , bits [ 7:0 ] = 0 x 01 : f = 2 octets per frame 0x455 0x0f or 0x1f register 0x455 , bits [4:0] = 0x0f or 0x1f: k = 16 or 32 frames per multiframe 0x456 0x00 register 0x456 , bits [7:0] = 0x00: m = 1 converter per link 0x457 0x0f register 0x457 , bits [7:6] = 0x0: always set cs = 0; register 0x457 , bits [4:0] = 0x0f: n = 16, always set to 16 - bit resolution 0x458 0x0f or 0x2f register 0x458 , bits [7:5] = 0x0 or 0x1: subclass 0 or subclass 1, register 0x458 , bits [4:0] = 0xf: np = 16 bits per sample 0x459 0x20 registe r 0x459 , bits [7:5] = 0x1: set to jesd204b version, register 0x459 , bits [4:0] = 0x0: s = 1 sample per converter per frame 0 x 45 a 0 x 00 register 0x45a, bit 7 = 0: hd = 0; register 0x45a , bits [ 4:0 ] = 0 x 00 : always set cf = 0 0x46c 0x01 register 0x46c , bits [7:0 ] = 0x01: des kew link lane 0 to link lane 7 0x476 0x02 register 0x476, bits [7:0] = 0x02: f = 2 octets per frame 0x47d 0x01 register 0x47d , bits [7:0] = 0x01: enable link lane 0 figure 67 . jesd204b mode 10 data deframing j19 j18 j1 j0 2 octets per lane 16-bit nibble group 1 sample per dac0 serial jesd204b data (l = 1) samples split across lanes (hd = 0) nibble group 0 serdin0 converter 0, sample 0 d15 ... d0 lane 0, octet 0 lane 1, octet 0 1 converter (m = 1) 1 1389-167 (f = 2) (n = 16) converter per frame (s = 1)
AD9154 data sheet rev. b | page 58 of 124 jesd204b test modes phy prbs testing the jesd204b receiver on the AD9154 includes a pseudorandom binary sequence (prbs) pattern checker on the back end of its physical layer. this functionality enables bit error rate (ber) testing of each physical lane of the jesd204b link. the phy prbs pattern checker does not require that the jesd204b link be established. it can synchronize with a prbs7, prbs15, or prbs31 data pattern. prbs pattern verification can be performed on multiple lanes at once. the error counts for failing lanes are reported for one jesd204b lane at a time. the process for performing prbs testing on the AD9154 is as follows: 1. start sending a prbs7, prbs15, or prbs31 pattern from the jesd204b transmitter. 2. select and write the appropriate prbs pattern to register 0x316, bits[3:2], as shown in table 57. 3. enable the phy test for all lanes being tested by writing to phy_test_en (register 0x315). each bit of register 0x315 enables the prbs test for the corresponding lane. for example, writing a 1 to bit 0 enables the prbs test for physical lane 0. 4. toggle phy_test_reset (register 0x316, bit 0) from 0 to 1, then back to 0. 5. set phy_prbs_error_threshold (register 0x319 to register 0x317) as desired. 6. write a 0 and then a 1 to phy_test_start (register 0x316, bit 1). the rising edge of phy_test_start starts the test. 7. wait 500 ms. 8. stop the test by writing 0 to phy_test_start (register 0x316, bit 1). 9. read the prbs test results. a. each bit of phy_prbs_test_status (register 0x31d) corresponds to one serdes lane. 0 = fail, 1 = pass. b. the number of prbs errors seen on each failing lane can be read by writing the lane number to check (0 to 7) in the phy_src_err_cnt (register 0x316, bits[6:4]) and reading phy_prbs_err_count (register 0x31a to register 0x31c). the maximum error count is 2 24 ? 1 . if all bits of register 0x31a to register 0x31c are high, the maximum error count on the selected lane has been exceeded. table 57. phy prbs pattern selection phy_prbs_pat_sel setting (register 0x316[3:2]) prbs pattern 0b00 (default) prbs7 0b01 prbs15 0b10 prbs31 transport layer testing the jesd204b receiver in the AD9154 supports the short transport layer (stpl) test as described in the jesd204b standard. use this test to verify the data mapping between the jesd204b transmitter and receiver. the stpl test ensures that each sample from each converter is mapped appropriately according to the number of converters (m) and the number of samples per converter (s). as specified in the jesd204b standard, the converter manufacturer specifies what test samples are transmitted. each sample must have a unique value. for example, if m = 2 and s = 2, four unique samples are transmitted repeatedly until the test is stopped. the expected sample must be programmed into the device and the expected sample is compared to the received sample one sample at a time until all have been tested. the process for performing this test on the AD9154 is described as follows: 1. synchronize the jesd204b link. 2. enable the stpl test at the jesd204b tx. 3. select converter 0 sample 0 for testing. write short_tpl_m_sel (register 0x32c, bits[3:2]) = 0 and short_tpl_sp_sel (register 0x32c, bits[5:4]) = 0. 4. set the expected test sample for converter 0, sample 0. program the expected 16-bit test sample into the short_tpl_ref_sp_x registers (register 0x32e and register 0x32d). 5. enable the stpl test. write 1 to short_tpl_test_en (register 0x32c, bit 0). 6. toggle the stpl reset, short_tpl_test_reset (register 0x32c, bit 1), from 0 to 1, then back to 0. 7. check for failures. read short_tpl_fail (register 0x32f, bit 0), 0 = pass, 1 = fail. 8. repeat steps 3 to step 7 for each sample of each converter. conv 0 sample 0 through conv m ? 1 sample s ? 1 . repeated cgs and ilas test as per section 5.3.3.8.2 of the jesd204b specification, the AD9154 can check that a constant stream of /k28.5/ characters is being received, or that a cgs followed by a constant stream of ilas is being received. to run a repeated cgs test, send a constant stream of /k28.5/ characters to the AD9154 serdes inputs. next, set up the device and enable the links as described in the device setup guide section. ensure that the /k28.5/ characters are being received by verifying that the syncoutx signal has been deasserted and that cgs has passed for all enabled link lanes by reading register 0x470. program register 0x300, bit 2 = 0 to monitor the status of lanes on link 0, and register 0x300, bit 2 = 1 to monitor the status of lanes on link 1 for dual link mode. to run the cgs followed by a repeated ilas sequence test, follow the device setup guide section, but before performing the last write (enabling the links), enable the ilas test mode by writing a 1 to register 0x477, bit 7. then, enable the links. when the device recognizes 4 cgs characters on each lane, it
data sheet AD9154 rev. b | page 59 of 124 read register 0x473 to verify that initial lane synchronization has passed for all enabled link lanes. pr ogram register 0x300, bit 2 = 0 to monitor the status of lane s on link 0, and register 0x300, bit 2 = 1 to monitor the status of lanes on link 1 for dual link mode. jesd204b error monit oring disparity, not in table, and unexpected control character errors p er s ection 7.6 of the jesd204b specification, the AD9154 can detect disparity errors, not in table errors, and unexpected control character errors, and can optionally issue a sync request and rei nitialize the link when errors occur. note that the disparity error counter counts all characters with invalid disparity, regardless of whether they are in the 8 - bit/10 - bit decoding table. this is a minor deviation from the jesd204b specification, which o nly counts disparity errors when they are in the 8 - bit/ 10 - bit decoding table. checking error counts the error count can be checked for disparity errors, not in table errors, and unexpected control character errors. the error counts are on a per lane and pe r error type basis. note that the lane select and counter select are programmed into register 0x46b and the error count is read back from the same address. to check the error count, complete the following steps: 1. select the desired link lane and error type of the counter to view. write these to register 0x46b according to table 58. to select a link lane, firs t select a link (register 0x300, bit 2 = 0 to select link 0 or register 0x300, bit 2 = 1 to select link 1 [dua l link only] ). note that , when using link 1, link lane x refers to logical lane x + 4. 2. read the error count from register 0x46b. note the maximum error count is equal to the error threshold set in register 0 x 47 c. table 58 . error c ounters addr. bits variable description 0 x 46b [ 6:4 ] lanesel lanesel = x to monitor the error count of link lane x. see the notes on link lane in step 1 of the checking error counts section. [ 1:0 ] cntrsel cntrse l = 0 b 00 for bad running disparity counter. cntrsel = 0 b 01 for not in table error counter. cntrsel = 0 b 10 for unexpected control character counter. check for error count over threshold in addition to reading the error count per lane and error type as described in the checking error counts section, the user can check a register to see if the error count for a given error type has reached a programmable threshold. the same error threshold is used for the three error types: disparity, not in table, and unexpected control character. the error counters are on a per error type basis. to use this feature, complete the following steps: 1. program the desired error count threshold into errorthres (register 0x47c). 2. read back the error status for each error type to see if the error count has reached the error threshold. disparity errors are reported in register 0 x 46d. not in table errors are reported in register 0 x 46 e. unexpected control character error s are report ed in register 0 x 46 f. error counter and irq control write to register 0x46d and register 0x46f to reset or disable the error counts and to reset the irq for a given lane. note that these are the same registers that are used to report error count over thre shold (see the check for error count over threshold section); thus, the readback is not the value that was written. for each error type , 1. select the link lane to access. to select a link lane, firs t select a link ( register 0x300, bit 2 = 0 to select link 0, r egister 0x300, bit 2 = 1 to select link 1 [dual link only] ). note that , when using link 1 , link lane x refers to logical lane x + 4 . 2. decide whether to reset the irq, disable the error count, and/or reset the er ror count for the given lane and error type. 3. write the link lane and desired reset or disable action to register 0x46d to register 0x46f according to table 59. table 59 . error counter and ir q control: disparity (register 0x46d), not in table (register 0x46e), unexpected control character (register 0x46f) bits variable description 7 rstirq rstirq = 1 to reset irq for the lane selected in bits[ 2:0 ]. 6 disable_errcnt disable_errcnt = 1 to disa ble the error count for the lane selected in bits[ 2:0 ]. 5 rsterrcntr rsteerrcntr = 1 to reset the error count for the lane selected in bits[ 2:0 ]. [ 2:0 ] laneaddr laneaddr = x to monitor the error count of link lane x. see the notes on link lane in step 1 of the checking error counts section.
AD9154 data sheet rev. b | page 60 of 124 monitoring errors via syncoutx when one or more disparity, not in table, or unexpected control character error occurs, the error is reported on the syncoutx pins as per section 7.6 of the jesd204b specification. the jesd204b specification states that the syncoutx signal is asserted for exactly 2 frame periods when an error occurs. for the AD9154 , the width of the syncoutx pulse can be programmed. the settings to achieve a syncoutx pulse of 2 frame clock cycles are given in table 60. table 60. setting syncoutx error pulse duration 1 these register settings assert the syncoutx signal for 2 frame clock cycles pulse widths. disparity, nit, unexpected control character irqs for disparity, not in table, and unexpected control character errors, error count over the threshold events are available as irq events. enable these events by writing to register 0x47a, bits[7:5]. the irq event status can be read at the same address (register 0x47a, bits[7:5]) after the irqs are enabled. errors requiring reinitializing a link reinitialization automatically occurs when four invalid disparity characters are received as per section 7.1 of the jesd specification. when a link reinitialization occurs, the resync request is 5 frames and 9 octets long. the user can optionally reinitialize the link when the error count for disparity errors, not in table errors, or unexpected control characters reaches a programmable error threshold. the process to enable the reinitialization feature for certain error types is as follows: 1. set threshold_mask_en (register 0x477, bit 3) = 1. note that when this bit is set, unmasked errors do not saturate at either threshold or maximum value. 2. enable the sync assertion mask for each type of error by writing to the sync_assertion_mask register (register 0x47b, bits[7:5]) according to table 61. 3. program the desired error counter threshold into errorthres (register 0x47c). 4. for each error type enabled in the sync_assertion_ mask register, if the error counter on any lane reaches the programmed threshold, syncoutx falls, issuing a sync request. note that all error counts are reset when a link reinitialization occurs. the irq does not reset and must be reset manually. table 61. sync assertion mask addr. bit no. bit name description 0x47b 7 baddis_s set to 1 to assert syncoutx if the disparity error count reaches the threshold 6 nit_s set to 1 to assert syncoutx if the not in table error count reaches the threshold 5 ucc_s set to 1 to assert syncoutx if the unexpected control character count reaches the threshold cgs, frame sync, checksum, and ilas monitoring register 0x470 to register 0x473 can be monitored to verify that each stage of jesd204b link establishment has occurred. program register 0x300, bit 2 = 0 to monitor the status of the lanes on link 0, and register 0x300, bit 2 = 1 to monitor the status of the lanes on link 1. bit x of codegrpsyncflag (register 0x470) is high if link lane x received at least 4 k28.5 characters and passed code group synchronization. bit x of framesyncflag (register 0x471) is high if link lane x completed initial frame synchronization. bit x of goodchksumflg (register 0x472) is high if the checksum sent over the lane matches the sum of the jesd204b parameters sent over the lane during ilas for link lane x. the parameters can be added either by summing the individual fields in registers or summing the packed register. if register 0x300, bit 6 = 0 (default), the calculated checksums are the lower 8 bits of the sum of the following fields: did, bid, lid, scr, l ? 1, f ? 1, k ? 1, m ? 1, n ? 1, subclassv, np ? 1, jesdv, s ? 1, and hd. if register 0x300, bit 6 = 1, the calculated checksums are the lower 8 bits of the sum of register 0x400 to register 0x40c and lid. bit x of initiallanesync (register 0x473) is high if link lane x passed the initial lane alignment sequence. cgs, frame sync, checksum, and ilas irqs fail signals for cgs, frame sync, checksum, and ilas are available as irq events. enable them by writing to register 0x47a, bits[3:0]. the irq event status can be read at the same address (register 0x47a, bits[3:0]) after the irqs are enabled. write a 1 to register 0x470, bit 7 to reset the cgs irq. write a 1 to register 0x471 to reset the frame sync irq. write a 1 to register 0x472 to reset the checksum irq. write a 1 to register 0x473 to reset the ilas irq. jesd204b mode ids pclockfactor (frames/pclock) syncb_err_dur (register 0x312[5:4]) setting 1 0, 4, 9 4 0 (default) 1, 2, 5, 6, 10 2 1 3, 7 1 2
data sheet AD9154 rev. b | page 61 of 124 configuration mismatch irq the AD9154 has a configuration mismatch flag that is avai lable as an irq event. use register 0x47b , bit 3 to enable the mismatch flag (it is enabled by defaul t), and then use register 0x47b, bit 4 to read back its status and reset the irq signal. see the interrupt request operation sec tion for more information. the configuration mismatch event flag is high when the link configuration settings (in register 0x450 to register 0x45d) do not match the jesd204b transmitted settings (register 0x400 to register 0x40d). all these registers are paged per link (in register 0 x 300). note that this function is different from the good checksum flags in register 0x472. the good checksum flags ensure that the transmitted checksum matches a calculated checksum based on the transmitted settings. the confi guration mismatch event ensures that the transmitted settings match the configured settings.
AD9154 data sheet rev. b | page 62 of 124 digital datapath figure 68. block diagram of the digital datapath figure 68 shows a block diagram of the signal processing digital datapath. the digital processing includes an input power detection block, three half-band interpolation filters, a quadrature modulator consisting of a fine resolution nco modulator and f dac /4 and f dac /8 coarse modulator blocks, an inverse sinc filter, and gain, phase, offset, and group delay adjustment blocks. the datapath is organized into two identical paths. each path processes a pair of digital signals input from the jesd204b transport layer block. the digital signals are processed by a datapath and input to a pair of dac cores. interpolation modes process the pair of signals as independent data streams. the coarse and fine modulation block requires that a data stream to be upconverted be an i/q pair of signals dual paging the digital datapath registers are paged to allow configuration of either dac dual independently or both simultaneously. table 62 shows how to use the dual paging register. table 62. paging modes pageindx reg. 0x008[1:0] duals paged dacs updated 1 a dac0 and dac1 2 b dac2 and dac3 3 (default) a and b dac0, dac1, dac2, and dac3 several functions are paged by dac dual, such as input data format, downstream protection, interpolation, modulation, inverse sinc, digital gain, phase offset, dc offset, group delay, iq swap, datapath prbs, lmfc sync, and nco alignment. data format binary_format (register 0x110, bit 7), paged as described in the dual paging section) controls the expected input data format. by default it is 0, which means the input data must be in twos complement. it can also be set to 1, which means input data is in offset binary (0x0000 is negative full scale and 0xffff is positive full scale). interpolation modes interpolation increases the sampling rate of a digital signal and can be bypassed. the transmit path contains three half-band interpolation filters, which each provide a 2 increase in the output sampling rate and a low-pass function. table 63 shows how to select each available interpolation mode, their usable bandwidths, and their maximum data rates. note that f data = f dac / interpolationfactor the maximum values of f data for interpolator bypass and the three interpolation factors are listed in table 2 as adjusted dac update rates; f data is another name for the adjusted dac update rate. interpolation mode is paged as described in the dual paging section. register 0x030, bit 0 is high if an unsupported interpolation mode is selected. table 63. interpolation modes and usable bandwidth interpolation mode interpmode reg. 0x112[2:0] usable bandwidth 1 (bypass) 0x00 0.5 x f data 2 0x01 0.4 f data 4 0x03 0.4 f data 8 0x04 0.4 f data 1 the maximum speed for 1 interpolation is limited by the jesd204b interface. filter performance interpolation modes increase the sampling rate of a digital signal by a factor of 2, 4, or 8. as part of the process, a digital low-pass filter is applied. the filter magnitude response for each interpolation mode is shown in figure 69. the usable bandwidth (as shown in table 63) is defined as the frequency band over which the filters have a pass-band ripple of less than 0.001 db and an image rejection of greater than 85 db. figure 69. all band responses of interpolation filters input power detection and protection coarse and fine modulation inv sinc digital gain and phase and offset adjustment 11389-032 0 ?20 ?40 ?60 ?80 ?100 0 0.2 0.4 0.6 0.8 1.0 magnitude (db) frequency ( f dac ) 11389-169 2 4 8
data sheet AD9154 rev. b | page 63 of 124 filter performance beyond specified bandwidth the usable pass band of the interpolation filter is specified as 0.4 f data . the filters can be used slightly beyond this ratio at the expense of increased pass - band ripple and decreased inter polation image rejection. figure 70 . interpolation filter performance beyond specified bandwidth figure 70 shows the performance of the interpolation filters beyond 0.4 f data . note that the ripple increases much slower than the image rejection decreases. this means that if the application can tolerate degraded image rejection from the interpolation filters, more bandwidth can be used. digital modulation the AD9154 includes modulation blocks that upconvert i/q quadrature signal pairs to an if frequency in the dig ital domain . the coarse modulation mode s ( f dac /4 and f dac /8) upconvert an i/q pair of digital signals to one of the selected ifs . the nco fine modulation mode upconvert s a n i/q sig nal pair to a n if fr equency programmed into the nco. modulation mode is sele cted as shown in table 64 and is paged as described in the dual paging section. table 64 . modulation mode selection modulation mode modulation_type register 0x111 , bits [3: 2 ] none 0b00 nco fine modulation 0b01 coarse ? f dac / 4 0b10 coarse ? f dac / 8 0b11 nco fine modulation this modulation mode uses the nco, a phase shifter, and a complex modulator to upconvert an i/q digital signal pair to an if frequency within the first nyquist zone of the dac cores. figure 71 shows a block diagram of the nco modulator . this allows output signals to be placed anywhere in the output spectrum with very fine frequency resolution. the nco produces a quadrature carrier to translate the input sign al to a new center frequency. a quadrature carrier is a pair of sinusoidal waveforms of the same frequency, offset 90 from each other. the frequency of the quadrature carrier is set via an ftw. the quadrature carrier is mixed with the i and q data and the n summed into the i and q datapaths, as shown in figure 71. ?f dac /2 f carrier < + f dac /2 ftw = ( f carrier / f dac ) 2 48 where ftw is a 48 - bit twos complement number. the frequency tuning word is set as shown in table 65 and paged as described in the dual paging section. table 65 . nco ftw registers address value description 0x114 ftw[ 7:0 ] 8 lsbs of ftw 0 x 115 ft w[ 15:8 ] next 8 bits of ftw 0 x 116 ftw[ 23:16 ] next 8 bits of ftw 0 x 117 ftw[ 31:24 ] next 8 bits of ftw 0 x 118 ftw[ 39:32 ] next 8 bits of ftw 0 x 119 ftw[ 47:40 ] 8 msbs of ftw unlike other registers, the ftw registers are not updated immediately upon writing. instead, the ftw registers update on the rising edge of ftw_update_req (register 0x113[0]). after an update request, ftw_update_ack (register 0x113[1]) must be high to acknowledge that the ftw has updated. sel_sideband (register 0x111, bit 1 ; paged as desc ribed in the dual paging section) is a convenience bit that can be set to use the negative modulation result. this is equivalent to flipping the sign of ftw. figure 71 . nco modulator blo ck diagram nco phase offset the nco phase offset feature allows rotation of the i and q phases. unlike phase adjust, this feature moves the phases of both i and q channels together. nco p hase offset can be used only when using nco fine modulation. ? 180 degreesoffset < +180 phaseoffset = ( degreesoffset /180 ) 2 15 where phaseoffset is a 16- bit twos complement number. the nco phase offset is set as shown in table 66 and paged as described in the dual paging section. because this function is 90 20 0 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 30 40 50 60 70 80 40 41 42 43 44 45 minimum interpolation image rejection (db) maximum pass-band ripple (db) bandwidth (% f data ) 11389-170 pass-band ripple image rejection interpolation interpolation nco 1 0 ?1 cos(n + ) sin(n + ) sine i data q data ftw[47:0] spectral inversion out_i out_q + ? nco phase offset [15:0] 11389-039
AD9154 data sheet rev. b | page 64 of 124 part of the fine modulation block, phase offset is not updated immediately upon writing. instead, it updates on the rising edge of ftw_ update_req (register 0x113, bit 0 ) along with th e f t w. table 66 . nco phase offset registers address value 0x11a nco_phase_offset [7:0] 0 x 11b nco_phase_offset[15:8] inverse sinc dacs have a sin(x)/x amplitude roll - off as a function frequency. this characteristic is shown in bl ue in figure 72. the AD9154 provides a digital inverse sinc function to compensate for this roll - off over frequency. the filter is enabled by setting the inv sinc_enable bit (register 0x111, bit 7, paged as described in the dual paging section) . inverse sinc is enabled by default. figure 72 shows the frequency response of sin (x)/x roll - off, the inverse sinc filter, and the composite response. the composite response has less than 0.05 db pass - band ripple up to a frequency of 0.4 f dacclk . to provide the necessary peaking at the upper end of the pass band, the inverse sinc fil ter shown has an intrinsic insertion loss of about 3.8 db; in many cases, this can be partially compensated as described in the digital gain section. figure 72 . responses of sin(x)/x roll - off, the sinc ?1 filter, and the composite of the two input signal power detection and protection digital gain, phase adjust, dc offset, a nd group delay digital gain, phase adjust, and dc offset (as described in the digital gain section, phase adjust section, and dc offset section) allow compensation of imbalances in the i and q paths due to analog mismatches between dac i/q outputs, quadrature modulator i/q baseba nd inputs, and dac/modulator interface i/q paths. these imbalances can cause the two following issues: ? an unwanted sideband signal appear s at the quadrature modulator output with significan t energy. cancel t his signal using digital gain and phase adjust. t uning the quadrature gain and phase adjust values can optimize complex image rejection in single sideband radios or can optimize the error vector magnitude (evm) in zero if (zif) architectures. ? the lo leakage at the output of a quadrature modulator followi ng the AD9154 in a signal chain can be cancelled by adjusting the dc current output of each dac driving modulator signal inputs. digital gain digital gain is used to independently adjust the digi tal signal magnitude being fed into each dac. the digital gain code can be left at its default value where it provide s 0 db of digital back off (in other words , a gain of 1) , o r it can be program med to provide larger digital backoff. digital gain can be pro grammed to introduce a n i/q pair gain imbalance to help a quadrature modulator following the AD9154 in a signal chain cancel an unwanted ssb sideband. digital gain is enabled by default and must n ot be disabled. t he amount of digital gain (gaincode) desired can be program - med in the registers shown in table 67. the d igital gain settings are described in the following equation s: 0 gain 4095/2048 ? db dbgain 6.018 db gain = gaincode (1/2048) dbgain = 20 log10( gain ) gaincode = 2048 gain = 2048 10 dbgain /20 where gaincode is a 12 - bit unsigned binary number. the i/q digital gain is set as shown in table 67 and paged as d escribed in the dual paging section. table 67 . digital gain registers addr. value description 0x111[5] dig_gain_enable set to 1 to enable digital gain at reset 0x13c gaincodei[7:0] i dac lsb gain code 0x13d gaincodei[11:8] i dac msb gain code 0x13e gaincodeq[7:0] q dac lsb gain code 0x13f gaincodeq[11:8] q dac msb gain code phase adjust ordinarily, the i and q channels of each dac pair have an angle of 90 between them. the phase adjus t feature changes the angle betwe en the i and q channels, which balance s the phase into a modulator. ? 14 degreesadjust < 14 phaseadj = ( degreesadjust /14) 2 12 where phaseadj is a 13 - bit twos complement number. the phase adjust is set as shown in table 68 and paged as described in the dual paging section. 1 0 magnitude (db) ?1 ?2 ?3 ?4 ?5 0 0.05 0.10 0.15 0.20 frequenc y ( f dac ) 0.25 0.30 0.35 0.45 0.40 0.50 11389-041 sin(x)/x roll-off sinc ?1 filter response composite response
data sheet AD9154 rev. b | page 65 of 124 table 68 . i/q phase adjustment registers addr. value description 0 x 111 [ 4 ] phase_adj_enable set to 1 to enable phase adjust 0x11c phaseadj[7:0] lsb phase adjust code 0 x 11d phaseadj[12:8] msb phase adjust code dc offset the dc offset feature is used to individually offset the data into the i or q dacs. this feature is used to cancel lo leakage at the modulator output . the offset is programmed individually for i and q as a 16 - bit twos complement number in lsbs, plus a 5 - bit twos complement number in sixteenths of an lsb, as shown in table 69 . dc offset i s paged as described in the dual paging section. ? 2 15 lsbsoffset < 2 15 ?16 sixteenthsoffset 15 table 69 . dc offset registers addr. value description 0x135[ 0] dc_offset_on set to 1 to enable dc offset 0x136 lsbsoffseti[7:0] i dac lsb dc offset code 0x137 lsbsoffseti[15:8 ] i dac msb dc offset code 0x138 lsbsoffsetq[7:0] q dac lsb dc offset code 0x139 lsbsoffsetq[15:8] q dac msb dc offset code 0x13a [4:0] sixteenthsoffseti i dac sub - lsb dc offset code 0x13b [4:0] sixteenthsoffsetq q dac sub - lsb dc offset code coarse gro up delay c oarse grou p del ay is a global adjustment of the da c latency, and it is programmed to identically a ffect both dacs in an i/q signal pair. the c oarse group delay range is in + 7 /? 8 steps. each step is ? dac clock cycle. the default value of 0x8 sets the delay to zero. this is useful in application s where the user needs to tune the latency of the dac path with some accuracy ( for example, in dpd loop delay adjust ) . write the value to coarse_ group_dly (register 0x014). this is paged as described in the dual paging sectio n. group delay compensation group delay compensat ion provides sepa rate delay tunability to either an i or q channel within e ach dual digital signal pair. the user can delay either the i or q output to align their quadrature. table 70 show s the registe r settings used for group delay co mpensation. the group delay comp ensation bypass register is locat ed a t register 0x 0 46. the groupdelaycomp (bits [7:0] ) values are binary , and t he default value of 0x00 is a delay compen sation of zero. the difference between this mode and the phase adjust mode is that group delay compensation can correct for delay differences between the i and q ch annels, while phase adjust cannot . group delay compensatio n is paged as described in the dual paging section. table 70. group delay compensation registers addr. value description 0x 046 group delay comp bypass set to 3 to bypass both i and q compensation 0x044 group delay comp i [7:0] 85 ps nominal range 0 x 045 group delay comp q [7:0] 85 ps nominal range i to q swap i_to_q (register 0x111, bit 0 ; paged as described in the dual paging section ) is a convenience bit that can be set to send the i datapath to the q dac. note that this swap occurs at the end of the datapath (after any modulation, digital gain, phase adjust, and phase offset). i f using m = 1 dacs in duallink m ode (as described in the dac power - down setup section), set this bit to direct data to the dac 3 output. nco alignment the nco alignment block phase align s the nco output from multipl e converters. two nco alignment modes are supported by the AD9154 . the first is a sysref alignment mode that phase aligns the nco outputs to the rising edge of a sysref pulse. the second alignme nt mode is a data key alignment; when this mode is enabled, the AD9154 aligns the nco outputs when a user specified data pattern arrives at the dac input. note that the nco alignment is per dual, and is paged as described in the dual paging section. sysref nco alignment as with the lmfc alignment, in subclass 1, a sysref pulse can be used to phase align the nco outputs of multiple devices in a system and multiple channels on the same device. note that in subclass 0, this alignment mode can be used to align the nco outputs within a device to an internal processing clock edge. no sysref edge is needed in subclass 0, but multichip alignment cannot be achieve d. the steps to achieve a sysref nco alignment are as follows: 1. set nco clr mode (register 0x050 , bits [1:0] ) = 0b01 for sysref nco alignment mode. 2. se t nco clr arm to 1 (register 0x050, bit 7 ). 3. perform an lmfc alignment to force the nco phase align (see the syncing lmfc signals section). the phase alignment occurs on the next sysref edge. note that if in one shot sync mode, the lmfc alignment block must be armed by setting register 0x03a, bit 6 = 1. if in continuous mod e or one shot then monitor mode, the lmfc align block does not need to be armed; the nco align automatically trips on the next sysref edge. 4. check the alignment status. if nco phase alignment was successful, nco clr pass (register 0x050, bit 4 ) = 1. if phase alignment failed, nco clr fail (register 0x050, bit 3 ) = 1.
AD9154 data sheet rev. b | page 66 of 124 data key nco alignment in addition to supporting the sysref alignment mode, the AD9154 supports a mode where the nco phase alignment oc curs when a user - specified pattern is seen at the dac input. the steps to achieve a data key nco alignment are as follows: 1. set nco clr mode (register 0x050 , bits [1:0]) = 0b10 . 2. write the expected 16 - bit data key for the i and q datapath into ncokeyi x (regist er 0x051 to register 0x052) and ncokeyq (register 0x053 to register 0x054), respectively. 3. se t nco clr arm (register 0x050, bit 7 ) = 1 . 4. send the expected 16- bit i and q data keys to the device to achieve nco alignment. 5. c heck the alignment status. if the expe cted data key was seen at the dac input, then nco clr mtch (register 0x050, bit 5 ) = 1. if nco phase alignment was successful, nco clr pass (register 0x050, bit 4 ) = 1. if phase alignment failed, nco_align_fail (register 0x050, bit 3 ) = 1 . multiple device nc o alignment can be achieved with the data key alignment mode. to achieve multichip nco alignment, program the same expected data key on all devices, arm all devices, and then send the data key to all devices/channels at the same time. nco alignment irq an irq event showing whether the nco align was tripped is available. use register 0x02 1 , bit 4 to enable dac dual a (dac0 and dac 1), and then use register 0x025, bit 4 to read back its status and reset the irq signal. use register 0x022, bit 4 to enable dac d ual b (dac2 and dac 3), and then use register 0x026, bit 4 to read back its status and reset the irq signal. see the interrupt request operation section for more information. downstream protectio n the AD9154 has several blocks designed to protect the power amplifier (pa) in its board level signal chain , as well as other downstream blocks. it consists of a power detection and protection (pdp) block, a blanking state machine (bsm), and a transmit enable state machine (tx en sm). the pdp block monitor s incoming data. if a moving avera ge of the data power goes above a threshold, the pdp block provides a signal (pdp_protect) that can be routed externally on the pdp out0 and pdp o ut1 pins . the tx en sm is a simpler block that controls delay betwee n txenx and the tx_protect signal. the tx_protect signal is used as an input to the bsm and its inverse can optionally be routed externally. optionally, the tx en sm can also power down its associated dac dual. the bsm gently ramps data entering the dac and flushes the datapath. the bsm is activated by the tx_protect signal or automatically by the lmfc sync logic during a rotation. d igital gain must be enabled for proper function . finally, some simple logic takes the outputs from each of those blocks and uses them to generate a desired pdp out x signal on an external pin. this signal can be used to enable/disable downstream components, such as a pa. power detection and protection the input signal pdp block detect s the average power of the dac input signal and to prevent overrange signals from being passed to the next stage, which may potentially cause destructiv e breakdown on power sensitive devices, such as pas. the protection function provides a signal (pdp_protect) that can be routed externally to shut down a pa. the pdp block uses a separate path with a shorter latency than the datapath to ensure that pdp_protect gets triggered before the overrange signal reaches the analog dac cores. the sum of the i 2 and q 2 are calculated as a representation of the input s ignal power (only the top seven msbs of data samples are used). the calculated sample power numbers are accumulated through a moving a verage filter whose output is the average of the input signal power in a certain number of samples. when the output of the averaging filter is larger than the threshold, the internal signal pdp_protect goes high, which can optionally be configured to trigg er a signal on the pdp out x pins . the pdp block is configured as shown in table 71 and paged as described in the dual paging section . the choice of pdp_avg_time (register 0 x062) and pdp_threshold [12:0] (register 0x060 to register 0x061) for effective protection are application dependent. experiment with real - world vectors to ensure proper configuration. the pdp_power[12:0] readback (register 0x063 to register 0x064) can help by storing the maximum power when a set threshold passes.
data sheet AD9154 rev. b | page 67 of 124 figure 73 . downstream protection block diagram table 71 . pdp registers addr. bit no. value description 0x060 [7:0] pdp_threshold[7:0] power that triggers pdp_protect. 8 lsbs. 0x061 [4:0] pdp_threshold[12:8] 5 msbs. 0x062 7 pdp_enable set to 1 to enable pdp. [ 3:0] pdp_avg_time can be set from 0 to 10. averages across 2 (9 + pdp_avg_time) , iq sample pairs. 0x063 [7:0] pdp_power[7:0] if pdp_t hreshold is crossed, this reads back the maximum power seen. if not, this reads back the instantaneous power. 8 lsbs. 0x064 [4:0] pdp_power[12:8] 5 msbs. power detection and protection irq the pdp_protect signal is available as an irq event. use registe r 0x021, bit 7 to enable pdp_protect for dual a (dac0 and dac1), an d then use register 0x025, bit 7 to read back its status and reset the irq signal. use register 0x022, bit 7 to enable pdp_protect for dual b (dac2 and dac 3), and then use register 0x026, b it 7 to read back its status and reset the irq signal. see the interrupt request operation section for more information. transmit enable state machine the tx en sm is a simple block that controls the delay between the txenx signal and the tx_protect signal. this signal is used as an input to the bsm and its inverse can be routed to an external pin ( pdp_out x) to turn downstream components on or off as desired. the txenx signal can be used to power down their associa ted dac duals . if d ac a_mask (register 0x012, bit 6 ) = 1, a falling edge of txenx causes dac dual a (dac0 and dac1) to power down . if dac b_mask (register 0x012, bit 7 ) = 1, a fal ling edge of txenx causes dac dual b (dac2 and dac3) to power down. on a rising edge of txenx, without daca _mask a nd dacb _mask enabled, the output is valid after the bsm settles (see the blanking state machine (bsm) section). if the masks are enabled, an additional delay is imposed; the outpu t is not valid until the bsm settles and the dacs fully power on (nominally an additional ~ 35 s). the tx ensm is configured as shown in table 72 and is paged as described in the dual paging section. table 72 . tx ensm registers addr. bit no. value description 0x11f [7:6] pa_fall number of fall counters to use (1 to 2). [5:4] pa_rise number of rise counters to use (0 to 2). 0x121 [7:0] rise_count_ 0 delay tx_protect rise from txen x rising edge by 32 rise_count_0 dac clock cycles. 0x122 [7:0] rise_count_1 delay tx_protect rise from txen x rising edge by 32 rise_count_1 dac clock cycles. 0x123 [7:0] fall_count_0 delay tx_protect rise from txen x r ising edge by 32 fall_count_0 dac clock cycles. must be at least 0x12. 0x124 [7:0] fall_count_1 delay tx_protect rise from txen x rising edge by 32 fall_count_1 dac clock cycles. 11389-173 filter and modulation digital gain pdp pdp_protect bsm bsm_protect tx_protect tx ensm data from lmfc sync logic txenx data to dacs pdp_protect_out 1 0 1 0 protect_out_invert protect_outx 1 0 tx_protect_out 1 0 spi_protect_out spi_protect protect outx generation
AD9154 data sheet rev. b | page 68 of 124 blanking state machine (bsm) the bsm gently ramps data entering the dac and flushes the datapath. on a falling edge of tx_protect (the txenx signal delayed by the tx ensm ), the datapath holds the latest data value and the digital gain gently ramps from its set value to 0. at the same time, the datapath is flu shed with zeroes. on a rising edge of tx_protect , the txenx signal is delayed by the tx ensm ; data is allowed to flow through the datapath again and the digital gain gently ramps the data from 0 up to the set digital gain. both of the abo ve functions are also triggered automatically by the lmfc sync logic during a rotation to prevent glitching on the output. ramping the step size to use when ramping gain to 0 or its assigned value can be controlled via the gain_ramp_down_step x registers (r egister 0x142 and register 0x143) and the gain_ramp_ up_step x registers (register 0x140 and register 0x141). these registers are paged as described in the dual paging section. the current bsm state can be read back as shown in table 73. table 73 . blanking state machine ramping readbacks address value description 0 x 147 [ 7:6 ] 0b00 data is being held at midscale. 0 b 01 ramping gain to 0. data ramping t o midscale. 0 b 10 ramping gain to assigned value. data ramping to normal amplitude. 0 b 11 data at normal amplitude. blanking state machine irq blanking completion is available as an irq event. use register 0x021, bit 5 to enable blanking completion for dac dual a ( dac0 and dac 1), and then use register 0x025, bit 5 to read back its status and reset the irq signal. use register 0x022, bit 5 to enable blanking completion for dac dual b (dac2 and da c3),and then use register 0x026, bit 5 to read back its sta tus and reset the irq signal. see the interrupt request operation section for more information. p dp outx generation register 0x013 controls which signals are ored into the external pdp out x signal. register 0x11f, bit 2 can be used to invert the pdp out x signal, by default, pdp out x is high when output is valid. both of these registers are paged as described in the dual paging section. table 74. p dp out x registers addr. bit no. description 0 x 013 6 1: pdp block triggers pdp_out 5 1: tx en sm triggers pdp_out 3 1: spi_protect triggers pdp_out 2 sets spi_protect 0 x 11f 2 inverts pdp out x datapath prbs the datapath prbs can be used to verify th at the AD9154 datapath is receiving and correctly decoding data. the datapath prbs verifies that the jesd204b parameters of the transmitter and receiver match, the lanes of the receiver are mapped appropriately, lanes have been appropriately inverted, if necessary, and in general that the start - up routine has been implemented correctly. the datapath prbs is paged as described in the dual paging section. to run the datapath prbs test, complete the following steps: 1. set up the device in the desired operating mode. see t he device setup guide section for details on setting up the device. 2. send prbs 7 or prbs 15 data. 3. write register 0x14b, b it 2 = 0 for prbs 7 or 1 for prbs 15. 4. write register 0x14b , bit 1 and bit 0 = 0 b 11 to enable and reset the prbs test. 5. write register 0x14b , bit 1 and bit 0 = 0 b 01 to enable the prbs test and release reset. 6. wait 500 ms. 7. check the status by checking the irq fo r dac0 to dac3 prbs as described in the datapath prbs irq section. 8. if there are failures, set register 0 x 008 = 0 x 01 to view the status of dual a (dac 0 /dac 1 ). set register 0 x 08 = 0 x 02 to view the status of dual b (dac 2 /dac 3 ). 9. read register 0x14b , bit 7 and bit 6 . bit 6 is 0 if the i dac o f the selected dual has any errors. bit 7 is 0 if the q dac of the selected dual has any errors. this must match the irq. 10. read register 0x14c to read the error count for the i dac of the selected d ual. read register 0x14d to read the error count for the q dac of the selected dual. note that the prbs processes 32 bits at a time, and compares the 32 new bits to the previous set of 32 bits. it detects (and reports) only 1 error in every group of 32 bit s, so the error count partly depends on when the errors are seen. for example , ? bits: 32 good, 31 good, 1 bad; 32 good (2 errors) ? bits: 32 good, 22 good, 10 bad; 32 good (2 errors) ? bits: 32 good, 31 good, 1 bad; 31 good, 1 bad; 32 good (3 errors)
data sheet AD9154 rev. b | page 69 of 124 datapath prbs irq the prbs fail signals for each dac are available as irq events. use register 0x020 , bits [3:0] to enable the fail signals, and then use register 0x024 , bits [3:0] to read back their statuses and reset the irq signals. see the interrupt request operation section for more information. dc test mode t he AD9154 provides a dc test mode . when dc test mod e is activated, the input to the digital data paths i s set to a mid scale dac input dc level in place of data from the jesd204b transpor t layer. dc test mode is en abled by setting register 0x520, bit 1 and clearing register 0x146 , bit 0 . register 0x146, bi t 0 must be set to 1 for all other modes of operation. in dc test mode, t he digital modulator can generate a sine wave at a fixed amplitude. digital g ain, dc offset , and phase adjustmen t can be applied to the sine wave on its way to each dac core input.
AD9154 data sheet rev. b | page 70 of 124 interrupt request op eration figure 74 . simplified schematic of irq circuitry the AD9154 provides an interrupt request output signal on pin 6 0 ( irq ) that can be used to notify an external host processor of significant device events. on assertion of the interrupt, query the device to determine the precise event that occurred. the irq pin is an open - drain, acti ve low output. pull the irq pin high external to the device. this pin can be tied to the interrupt pins of other devices with open - drain outputs to wire; or these pins together . figure 74 shows a simplified block diagram of how the irq blocks works. if irq_en is low, the interrupt_source signal is set to 0. if irq_en is high, any rising edge of event causes the interrupt_source signal to be set high. if any interrupt_source signal is high, the irq pin is pulled low. interrupt_source can be reset to 0 by either an irq_reset signal or a device_reset. depending on status_mode, the event_status bit reads back event or interrupt_source. the AD9154 has several irq register blocks, which can monitor up to 75 events (depending on device configuration). certain details vary by irq register block as described in table 75. table 76 shows which registers the irq_en, irq_reset, and status_mode signals in figure 74 are coming from, as well as the address where event_status is read back. table 75 . irq register block details register block event reported event_status 0 x 01 f to 0 x 026 per chip interrupt_source if irq is enabled, if not, it is event 0 x 46 d to 0 x 46 f; 0 x 470 to 0 x 473; 0 x 47 a per link and lane interrupt_source if irq i s enabled, if not, 0 0 x 47b[ 4 ] per link interrupt_source if irq is enabled, if not, 0 interrupt service ro utine interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. enable the events that re quire host action so that the host is notified when they occur. for events requiring host intervention upon irq activation, run the following routine to clear an interrupt request: 1. read the status of the event flag bits that are being mo nitored. 2. disable the interrupt by writing 0 to irq_en. 3. read the event source. for register 0 x 01 f to register 0 x 026 , event_status has a live readback. for other events, see their registers. 4. perform any actions that may be required to clear the cause of the event . in many cases, no specific actions may be required. 5. verify that the event source is functioning as expected. 6. clear the interrupt by writing 1 to irq_reset. 7. enable the interrupt by writing 1 to irq_en. 11389-043 irq_en event device_reset event_status interrupt_source irq_en status_mode 1 0 1 0 other interrupt sources irq irq_reset
data sheet AD9154 rev. b | page 71 of 124 table 76 . irq register block address of irq signal details register block address of irq signals irq_en irq_reset status_mode event_status 0 x 01 f to 0 x 026 0 x 01 f to 0 x 022 ; r/w per chip 0 x 023 to 0 x 026 ; w per chip status_mode = irq_en 0 x 023 to 0 x 26 ; r per chip 0 x 46 d to 0 x 46 f 0 x 47 a; w per link 0 x 46 d to 0 x 46 f; w per link and lane n ot applicable , status_mode = 1 0 x 47 a; r per link 0 x 470 to 0 x 473 0 x 47 a; w per link 0 x 470 to 0 x 473 ; w per link n ot applicable , status_mode = 1 0 x 47 a; r per link 0 x 47b[ 4 ] 0x47b[3]; r/w per link; 1 by def ault 0 x 47b[ 4 ]; w per link n ot applicable , status_mode = 1 0 x 47b[ 4 ]; r per link
AD9154 data sheet rev. b | page 72 of 124 dac input clock conf igurations the AD9154 dac sample clock or device clock (dacclk) can be sourced directly through clk (pin 2 and pin 3) or by using on - chip clock multipl ication with the same clk differential input serving as the reference . clock multiplying employs the on - chip dac pll that accepts a reference clock operating at a submultiple of the desired dacclk rate. the pll then multiplies the reference clock up to the desired dacclk frequency, which is then used to generate all the clocks within the AD9154 . driving the clk inp uts the clk differential input is shown in figure 75 . the on - chip clock receiver has a differential input impedance of 10 k?. clk are not terminated on chip; the inpu ts are self biased to a common - mode voltage of 600 mv. the inputs can be driven by differential pecl or lvds drivers with ac coupling between the clock source and the receiver. a ty pical 100 ? differential b oard level termination resistor is placed between the ac coupling capacitors and the clk pins . f igure 75 . clock receiver input simplified equivalent circuit dac pll fixed register writes to optimize the pll across all operating conditions, the following spi writes are recommended : 0x087 = 0x62, 0x088 = 0xc 9, 0x089 = 0x0e, 0x08a = 0x12, 0x08d = 0x7b, 0x1b 0 = 0x00, 0x1b 5 = 0xc9, 0x1b 9 = 0x24, 0x1bc = 0x0d, 0x1be = 0 x02, 0x1bf = 0 x8e , 0x1c 0 = 0x2a, 0x1c 4 = 0x7e , and 0x1c 5 = 0x 06. these writes properly set up the dac pll, including the loop filter and the charge pump . loop filter the rf pll filter is fully integrated on - chip and is a standard passive third - order filter with five 4 - bit programmable components (see figure 76 ). the c1, c2, c3, r1, and r3 filter components are programmed in as listed in dac pll fixed register writes in the dac pll fixed register writes sec tion to register 0x087, register 0x088, and register 0x 089. f igure 76 . loop filter charge pump the charge pump current is 6 - bit programmable variable with a range of 0.1 ma to 6.4 ma. it is programmed in register 0x08a , bits[5:0] as shown in the dac pll fixed register writes section. the charge pump is automatically calibrated t he first time the dac pll is enabled. the charge pump calibration raises bit 5 of register 0x084 after it is comp lete and valid. f igure 77 . charge pump condition specific r egister writes clock multiplication relationships the on - chip pll clock multiplier circuit can be used to generate the dac sample rate clock from a lower frequency refere nce clock. the pll is integrated on chip. the pll vco operates over a frequency range of 6 ghz to 12 ghz. the pll configuration parameters must be programmed before the pll is enabled. step by step instructions on how to program the pll can be found in the starting the pll secti on. a f unctional block diagram of the clock multiplier is shown in figure 78. when in use, the clock multiplication circuit generates the dac samplin g clock from the reference clock ( refclk ) input . the frequency of the refclk ( clk ) input is referred to as f ref . the refclk input is divided by the variable refdivfactor. select the refdivfactor variable to ensure that the frequency into the phase frequen cy detector (pfd) block is between 35 mhz and 80 mhz. the valid values for refdivfactor are 1, 2, 4, 8, 16, or 32. each refdivfactor maps to the appropriate refdivmode register control according to table 77. the re fdivmode register is programmed through register 0x08c , bits [2:0]. table 77 . mapping of refdivfactor to refdivmode dac reference frequency range (mhz) divide by (refdivfactor) refdivmode register 0x08c , bits [2:0] 35 to 80 1 0 80 to 160 2 1 160 to 320 4 2 320 to 640 8 3 640 to 1000 16 4 clk+ clk? 600mv 5k? 5k? 11389-044 r1 from charge pum p t o vco t o vco ldo c1 c2 c3 r3 11389-045 up down charge pum p current = 0.1m a t o 6.4m a t o loo p fi lter 1 1389-046
data sheet AD9154 rev. b | page 73 of 124 use the following equation to determine the refdivfactor : mhz 80 mhz 35 < < or refdivfact f ref (1) where: refdivfactor is the reference divider division ratio. f ref is the reference frequency on the clk in put pins. the bcount value is the divide ratio of the loop divider. it is set to divide the f dacclk to frequency match the f ref /refdivfactor. select bcount so that the following equation is true: or refdivfact f bcount f ref dacclk = 2 (2) where: bcount is the feedback loo p divider ratio. f dacclk is the dac sample clock frequency . the bcount value is programmed using bits[ 7:0 ] of register 0 x 085 . it is programmable from 6 to 127. the pfd compares f ref / refdivrate to f dac /(2 bcount ) and pulses the charge pump up or down to c ontrol the frequency of the vco. the clock multiplication circuit operates such that the vco outputs a frequency, f vco . f vco = f dacclk lodivfactor (3) and from equation 2, the dac sample clock frequency, f dacclk , is equal to or refdivfact f bcount f ref dacclk = 2 (4) th e lodivfactor is chosen to keep f vco in the operating range between 6 ghz and 12 ghz. the valid values for lodivfactor are 4, 8, and 16. each lodivfactor maps to a lodivmode value. the lodivmode (register 0x08b[1:0]) is programmed as described in table 78. table 78 . dac vco divider selection dac frequency range (mhz) divide by (lodivfactor) lodivmode register 0x08b , bits [ 1:0 ] > 1500 4 1 750 to 1500 8 2 420 to 750 16 3 table 79 lists some common frequency examples for the refdivfactor, lodivfactor, and bcount values that are needed to configure the pll properly. table 79 . common frequency examples frequency (mhz) f dac clk (mhz) f vco (mhz) refdiv ? factor lodiv ? factor bcount 368.64 1474.56 11796.48 8 8 16 184.32 1474.56 11796.48 4 8 16 307.2 1228.88 9831.04 8 8 16 122.88 983.04 7864.35 2 8 8 61.44 983.04 7864.35 1 8 8 491.52 1966.08 7864.35 8 4 16 245.76 1966. 08 7 864.35 4 4 16 table 79 include s different parameter sets based on f vco . the correct value to use is determined by the frequency into the p hase f requency d etector block of the pll. temperature tracking when properly configured, the device automatically selects one of the 512 vco bands. the pll settings selected by the device ensure that the pll remains locked over the full ?40c to +85c operating temperature range of the device without further adjustment. the pll remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes. to properly configure temperatu re tracking, follow the settings in the dac pll fixed register writes section and the f vco dependent spi writes shown in table 80. table 80. vco control lookup table reference vco frequency range ( g hz) register 0x1b4 setting register 0x1b6 setting register 0x1bb setting f vco < 6.85 0x60 0x49 0x15 6.85 f vco < 8.72 0x60 0x49 0x13 8.72 f vco < 10.7 0x60 0x4d 0x13 f vco 10.7 0x78 0x4d 0x04 starting the pll the programming sequence for the dac pll is as follows: 1. use the equations in the clock multiplication relationships section to find f vco , f ref , bcount, refdivmode , and lodivmode . 2. program the registers in the dac pll fixed register writes section. 3. program lodivmode in to register 0x08b , bits [ 1:0 ]. 4. program the bcount in register 0x085 , bits [7:0 ]. 5. program refdivmode in register 0x08c , bits [2:0]. 6. based on the f vco found in step 1 , write the temperature tracking registers as shown in table 80. 7. enable the dac pll synthesizer by setting register 0x083 , bit 4 to 1 .
AD9154 data sheet rev. b | page 74 of 124 registe r 0x084, bit 5 notifies the user that the dac pll calibration is completed and is valid. register 0x084, bit 1 notifies the user that the pll has locked. register 0x084, bits[ 7 :6] and register 0x084, bit 5 notify the user that the dac pll hit the upper or lower edge of its operating band, respectively . if either of these bits are high, recalibrate the da c pll by setting register 0x083, bit 7 to 0 and then 1. dac pll irq the dac pll lock and lost signals are available as irq events. use register 0x01f , bit 5 and bit 4 to enable these signals, and then use register 0x023 , bit 5 and bit 4 to read back their statuses and reset the irq signals. see the interrupt request operation section. figure 78 . device clock pll block diagram lc vco 6ghz to 12ghz 4-bit programmable, integrated loop filter charge pump pfd 80mhz max retimer up down f ref 30mhz to 1ghz b counter n1 = divide by 1, 2, 4, 8, 16, 32 0.1ma to 6.4ma fo cal alc cal cal control bits r1 r3 c1 c2 c3 vco ldo mux/selectable buffers 2 2 i q i q i q 2 2 1.5ghz to 3ghz 3ghz to 6ghz 750mhz to 1.5ghz 375mhz to 750mhz dac clock maximum frequency = 1.6ghz n mux = 4, 8, 16 1 1389-047 2 2 4 8 16
data sheet AD9154 rev. b | page 75 of 124 analog outputs transmit dac operati on figure 79 shows a simplified block diagram of the transmit path dac cores . there are four dac cores: dac0 and dac2 are designated i dacs; dac1 and d ac3 are designated q dacs. the dac core s consist of a current switch array, digital control logic, and full - scale output current control. the dac full - scale output current (i outfs ) is defined in table 1 . the output currents from t he outx pins are complementary, meaning that the sum of the two currents always equals the full - scale current of the dac. outx are current sinks. current flows into the outx ports. the digital input code to the dac dete rmines the differential current ou tput . figure 79 . simplified block diagram of the dac core a 4 k external resistor, r set , must be connected from the i120 pin to ground . this resistor, along with the reference control amplifier, sets up the correct internal bia s currents for each dac core . the full - scale current equation, where the dac gain is set for each i dac core pair and each q dac core pair in register s 0x 0 40 through register 0x 0 43 is as follows: ? ? ? ? ? ? ? ? ? ? ? ? + = dac gain r v i set ref outfs 19 . 19 1 33 . 13 (5) figure 80 is a plot of i outfs as a function of dac_gain_ix and dac_gain_qx figure 80 . dac full - scale current (i outfs ) vs. dac gain code transmit dac transfer function the output currents drawn by the outx+ and outx? pins are complementary, meaning that the sum of the two (positive plus negative) currents always equals the full - scale current of the dac , i outfs . the digital input code to a dac determines the differential current output . the outx+ pin s provide the maximum output current when all bits are high. the output currents vs. daccode for the dac outputs are expressed as outfs n outp i daccode i ? ? ? ? ? ? = 2 (6 ) outp outfs outn i i i ? = daccode = 0 to 2 n ? 1 and is the digital signal input to a dac cor e c onsisting of a stream of 16 bit samples . out3+ out3? out2+ out2? out1+ out1? out0+ out0? current scaling i dacs full-scale adjust q dacs full-scale adjust 1.2v n? i 20 dac3 dac2 dac1 dac0 1 1389-048 0 5 10 15 dac gain code 20 25 0 64 128 192 256 320 384 448 dac full-scale current (i outfs ) 512 576 640 704 768 832 896 960 1024 1 1389-050
AD9154 data sheet rev. b | page 76 of 124 normal and mix modes of operation figure 81 . two - switch and quad - switch dac waveforms the dac cores have a quad - switch architecture . during each dacclk cycle , one input sample is presented twice. figure 81 shows the time domain dac core output when operating in normal mod e (default) . in normal mode , the same output signal is presented twice during each dac clock cycle . the dac output mod e is selected using b it 0 of register 0x04a . figure 82 depicts a time domain dac output signal in mix mode. during each dacclk cycle, the input sample is presented at the output on the rising edge and the inverse o f the input sample is presented at the output on the falling edge of dacclk. figure 82 . mix mode waveform figure 83 is a depiction of the uncompensated d ac sinc roll - off for normal (or b aseband) m ode and for mix m ode. in normal mode, the first n yquist zone copy of the output signal has the highest amplitude. the output sampling images in the second and thir d nyquist zones are attenuated. in mix mode, the second and third nyquist zone samp ling images are emphasized , and the first nyquist zone signal is attenuated. this ability to change modes provides the user the flexibility to place a carrier anywhere in the first three nyquist zones, depending on the operating mode selected. swi tching be tween baseband and mix mod e reshapes the sinc roll - off inherent at the dac output. figure 83 . sinc roll - off for normal mode and mix - mode operation input data dacclk two-switch dac output quad-switch dac output (normal mode) t d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 6 d 7 d 8 d 9 d 1 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 d 2 d 3 d 4 d 5 t 1 1389-181 input data dacclk quad - sw i t c h d ac o u t pu t ( f s m i x m o d e) ? d 6 ? d 7 ? d 8 ? d 9 ? d 1 0 d 6 d 7 d 8 d 9 d 1 0 ? d 1 ? d 2 ? d 3 ? d 4 ? d 5 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 d 2 d 3 d 4 d 5 t 1 1389-182 normalized f r e q u e nc y relative to f dacclk ( h z) 0 1 . 5 0 1 . 2 5 1 . 0 0 0 . 75 0 . 50 0 . 25 ? 3 5 ? 3 0 ? 2 5 ? 2 0 ? 1 5 ? 1 0 ? 5 0 f i r s t n y q u i s t z o n e se c o n d n y q u i s t z o n e t h i r d n y q u i s t z o n e m i x m o d e output current (dbfs) baseband m o d e 1 1389-183
data sheet AD9154 rev. b | page 77 of 124 temperature sensor the AD9154 has a band gap temperature sensor for monitoring junction temperature changes on the AD9154 die. the temperature must be calibrated against a known temperature to remove the device-to-device variation in the band gap circuit used to sense the temperature. to monitor temperature change, the user must take a reading at a known ambient temperature for a single-point calibration of each AD9154 device. tx = t ref + 7.3 ( code_x ? code_ref )/1000 where: code_x is the die_temp readback code from register 0x132 and register 0x133 at the unknown temperature, tx . code_ref is the die_temp readback from the same addresses at the calibrated temperature, t ref . to use the temperature sensor, it must be enabled by setting register 0x12f, bit 0, to 1. the user must write a 1 to register 0x134, bit 0 before reading back the die temperature from register 0x132 and register 0x133.
AD9154 data sheet rev. b | page 78 of 124 example start - up sequence table 81 through table 90 show the register wri tes needed to set up the AD9154 with f dac = 1474.56 mhz, 2 interpolation, and the dac pll enabled with a 368.64 mhz reference clock. the jesd204b interface is configured in mode 4, dual link mode , subclass 1, and scrambling is enabled with all eight serdes lanes running at 7.3728 gbps, inputting twos complement for - matted data. no remapping of lanes with the crossbar is performed in this example. the sequence of steps to properly start up the AD9154 is as follows: 1. set up the spi interface, power up necessary circuit blocks, make required writes to the configuration register, and set up the dac clocks (see step 1: start up the dac ). 2. set the digital features of the AD9154 (see step 2: digital datapath ). 3. set up the jesd204b links (see step 3: transport layer ). 4. set up the physical layer of the serdes interface (see step 4: physical layer ). 5. set up the data link layer of the serdes interface. this procedure is for quick s tartup or debug only and does not guarantee deterministic latency (see step 5: data link layer ). 6. check for errors on link 0 and link 1 (see step 6 : error monitoring ). these steps are outlined in detail in the following sections , with in tables that list the required register write and read commands. step 1: start up the dac power - up and dac initialization table 81 . power - up and dac initialization comm and address value description w 0x000 0xbd soft reset w 0x000 0x3c deassert reset, set 4 - wire spi w 0x011 0x00 enable reference, dac channels, and master dac w 0x080 0x0 4 power up all clocks with duty cycle correction on w 0x081 0x00 power up sysref receiver, disable hysteresis required device configurations table 82 . required device configuration command address value description w 0 x 12d 0 x 8 b digital datapath configuration w 0 x 146 0 x 01 digital datapath configuration w 0x 333 0x01 jesd interface configuration configure the dac pll table 83 . configure dac pll command address value description w 0 x 087 0x62 optimal dac pll loop filter settings w 0 x 088 0xc9 optimal dac pll loop filter settings w 0 x 089 0x0e optimal dac pll loop filter settings w 0 x 08a 0x12 optimal dac pll cp settings w 0x08d 0x7b optimal dac ldo settings for dac pll w 0x1b0 0x00 power dac pll blocks when power machine disabled w 0x1b5 0xc9 optimal dac pll vco settings w 0x1b9 0x24 optimal dac pll calibration options settings w 0x1bc 0x0d optimal dac pll block control settings w 0x1be 0x02 optimal dac pll vco power control settings w 0x1bf 0x8e optimal dac pll vco calibration settings w 0x1c0 0x2a optimal dac pll lock counte r length setting w 0x1c1 0x2a optimal dac pll cp setting w 0x1c4 0x7e optimal dac pll varactor settings w 0x1c5 0x06 optimal dac pll vco settings w 0x08b 0x02 set the vco lo divider to 8 so that 6 ghz f vco = f dacclk 2 (lodivmode + 1) 12 ghz w 0x 08c 0x03 set the reference clock divider w 0x085 0x10 set the b counter to 16 to divide the dac clock down to 2 the reference clock w 0 x 1b6 0x4d write vco varactor settings from table 80 w 0 x 1bb 0x04 write vco bias reference and tc from table 80 w 0 x 1b4 0x78 write vco calibration offset from table 80 w 0 x 1c5 0x0 6 write vco varactor reference w 0x083 0x10 enable dac pll r 0x084 0x01 verify that bit 1 reads back high for pl l locked step 2: digital data path table 84 . digital datapath command address value description w 0x112 0x01 set the interpolation to 2 w 0 x 110 0 x 00 set twos complement data format
data sheet AD9154 rev. b | page 79 of 124 step 3: transport la yer table 85 . link 0 transport layer command address value description w 0x200 0x00 power up the interface w 0x201 0x00 enable all lanes w 0x300 0x08 bit 3 = 1 for dual link, bit 2 = 0 to access link 0 registers w 0x450 0x00 set the device id to match tx (0x00 in this example) w 0x451 0x00 set the bank id to match tx (0x00 in this example) w 0x452 0x00 set the lane id to match tx (0x00 in this example) w 0x453 0x83 set descrambling and l = 4 ( in n ? 1 notation) w 0x454 0x00 set f = 1 ( in n ? 1 not ation) w 0x455 0x1f set k = 32 ( in n ? 1 notation) w 0x456 0x01 set m = 2 ( in n ? 1 notation) w 0x457 0x0f set n = 16 ( in n ? 1 notation) w 0x458 0x2f set subclass 1 and np = 16 ( in n ? 1 notation) w 0 x 459 0x20 set jesd 204b version and s = 1 ( in n ? 1 notation) w 0x45a 0x80 set hd = 1 w 0x45d 0x45 set checksum for lane 0 w 0x46c 0x0f deskew lane 0 to lane3 w 0x476 0x01 set f (not in n ? 1 notation) w 0x47d 0x0f enable lane 0 to lane 3 table 86 . link 1 transport layer command address value description w 0x300 0x0c bit 3 = 1 for dual link, bit 2 = 1 to access registers for link 1 w 0x450 0x00 set the device id to match tx (0x00 in this example) w 0x451 0x00 set the bank id to match tx (0x00 in this ex ample) w 0 x 452 0x04 set the lane id to match tx (0x04 in this example) w 0x453 0x83 set descrambling and l = 4 ( in n ? 1 notation) w 0x454 0x00 set f = 1 ( in n ? 1 notation) w 0x455 0x1f set k = 32 ( in n ? 1 notation) w 0x456 0x01 set m = 2 ( in n ? 1 notation) w 0x457 0x0f set n = 16 ( in n ? 1 notation) w 0x458 0x2f set subclass 1 and np = 16 ( in n ? 1 notation) w 0x459 0x20 set jesd 204b and s = 1 ( in n ? 1 notation) w 0x45a 0x80 set hd w 0x45d 0x45 set checksum for lane 0 w 0x46c 0x0f deskew lane 4 to lane 7 0x476 0x01 set f (not in n ? 1 notation) w 0x47d 0x0f enable lane 4 to lane 7 step 4: physical la yer table 87 . physical layer command address value description w 0x2a7 0x01 autotune phy setting w 0x2ae 0x01 autotune phy setting w 0x314 0x01 serdes spi configuration w 0x230 0x28 configure cdrs in half rate mode w 0x206 0x 00 resets cdr logic w 0x206 0x01 release cdr logic reset w 0x289 0x04 configure pll divider to 1 along with pll required configuration w 0x284 0x62 optimal serdes pll loop filter w 0x285 0xc9 optimal serdes pll loop filter w 0x286 0x0e optimal serdes pll loop filter w 0x287 0x12 optimal serdes pll charge pump w 0 x28a 0x7b optimal serdes pll vco ldo w 0x28b 0x00 optimal serdes pll pd w 0x290 0x8 9 optimal serdes pll vco w 0x291 0x4c optimal serdes pll vco w 0x294 0x24 optimal serdes pll charge pump w 0x296 0x 1b optimal serdes pll vco w 0x297 0x0d optimal serdes pll vco w 0x299 0x02 optimal serdes pll pd w 0x29a 0x8e optimal serdes pll vco w 0x29c 0x2a optimal serdes pll charge pump w 0x29f 0x7e optimal serdes pll vco w 0x2a0 0x0 6 configure se rdes pll vco w 0x280 0x01 enable serdes pll r 0x281 0x01 verify that bit 0 reads back high for serdes pll lock w 0x268 0x62 set equalizer mode to low power
AD9154 data sheet rev. b | page 80 of 124 step 5: data link la yer note that this procedure does not guarantee deterministic latency. tab le 88 . data link layer (does n ot guarantee deterministic latency ) command address value description w 0x301 0x01 set subclass = 1 w 0x304 0x00 set the lmfc delay setting to 0 w 0x305 0x00 set the lmfc delay setting to 0 w 0x306 0x0a set the lmfc receive buffer delay to 10 w 0x307 0x0a set the lmfc receive buffer delay to 10 w 0x03a 0x01 set sync mode to one - shot sync w 0x03a 0x81 enable the sync machine w 0x03a 0xc1 arm the sync machine sysref ensure that at least one sy sref edge is sent to the device w 0x300 0x0b bit 1 and bit 0 = 1 to enable link 0 and link 1, bit 2 = 0 to access link 0 step 6: error monito ring link 0 checks confirm that the registers in table 89 read back a s noted and system tasks are completed as described. table 89 . link 0 checks command address value description r 0x470 0x0f acknowledge that four consecutive k28.5 characters have been detected on lane 0 to lane 3. syncout0 confirm that syncout0 is high. serdinx apply ilas and data to the serdes input pins. r 0x471 0x0f check for frame sync on all lanes. r 0x472 0x0f check for good checksum. r 0x473 0x0f check for ilas. link 1 chec ks confirm that the registers in table 90 read back as noted and system tasks are completed as described . table 90 . link 1 checks command address value description w 0x300 0x0f bit 2 = 1 t o access link 1. r 0x470 0x0f acknowledge that four consecutive k28.5 characters have been detected on lane 4 to lane 7. syncout1 confirm that syncout1 is high. serdinx apply ilas and data to the serdes input pins. r 0x471 0x0f check for frame sync on all lanes. r 0x472 0x0f check for good checksum. r 0x473 0x0f check for ilas.
data sheet AD9154 rev. b | page 81 of 124 board level hardware considerati ons power supply recomme ndations figure 84 . power supply connections table 91 . power supplies power supply domain voltage (v) circuitry dvdd12 1 1.2 digital core pvdd12 2 1.2 dac pll svdd12 3 1.2 jesd 204 b receiver interface cvdd12 1 1.2 dac clocking iovdd 3.3 spi interface v tt 4 1.2 v tt siovdd 33 3.3 sync lvds transmit avdd 33 3.3 dac 1 t his supply requires a 1.3 v supply when operating at maximum dac sample rates. see table 3 f or details. 2 this supply may be combined with cvdd12 on the same regulator with a separate supply filter network and sufficient bypass cap acitors near the pins. 3 t his supply requires a 1.3 v supply when operating at maximum interface rates. see table 4 for details. 4 t his supply is connected to svdd12 and does not need separate circuitry. the power supply domains are described in table 91 . the power supplies can be grouped into separate pcb domains as show in figure 84 . all the AD9154 supply domains must remain as noise free a s possible . optimal dac output nsd and dac output phase noise performance can be achieved using linear regulators that provide excellent power supply rejection. avdd33, pvdd12, and cvdd12 are particularly sensitive to supply noise. jesd204b serial inte rfac e inputs (serdin0 to serdin7) when considering the layout of the jesd204b serial interface transmission lines, there are many factors to consider to maintain optimal link performance. among these factors are insertion loss, return loss, signal skew, and the topology of the differential traces. insertion loss the jesd204b specification limits the amount of insertion loss allowed in the transmission channel (see figure 44 ). the AD9154 equalization circuitry allows significantly more loss in the channel than is required by the jesd204b specification. it is still important that the designer of the pcb minimize the amount of insertion loss by adhering to the following guidelines: ? keep the differential traces short by placing the AD9154 as near to the transmitting logic device as possible and routing the trace as directly as possible between the devices. ? route the diffe rential pairs on a single plane using a solid ground plane as a reference. ? use a pcb material with a low dielectric constant (< 4 ) to minimize loss, if possible. w hen choosing between stripline and microstrip techniques, consider the following : stripline ha s less loss (see figure 45 ) and emits less emi, but requires the use of vias that can add complexity to the ta sk of controlling the impedance, whereas microstrip (see figure 46 ) is easier to implement if the component placement and density allow routing on the top layer and eases the task of controlling the impedance. if using the top layer of the pcb is problematic or the advantages of stripline are desirable, follow these recommendations: ? minimize the number of vias. ? if possible, use blind vias to eliminate via stub effects and use micro vias to minimize via inductance. power input +12v +3.3v AD9154 adm7154-3.3 adm7160-3.3 adp1753 adp2119 adp1741 adp1741 adp2370 svdd12 dvdd12 cvdd12 + pvdd12 avdd33 iovdd + siovdd33 3.8v 1.8v step down dc/dc 1.2mhz, 2a buck 1.2mhz/600khz 800ma 1.2v 1.2v 1.2v 3.3v 3.3v 1 1389-184
AD9154 data sheet rev. b | page 82 of 124 ? if using standard vias, use the maximum via length to minimize the stub size. for example, on an 8 - layer board, use layer 7 for the stripline pair (see figure 85) . ? for each via pair, place a pair of ground vias adjacent to them to minimize the impedance discontinuity (see figur e 85) . figure 85 . minimizing stub effect and adding ground vias for differential stripline traces return loss the jesd204b specification limits the amount of return loss allowed in a converter device and a logic device, but doe s not specify return loss for the channel. however, every effort must be made to maintain a continuous impedance on the transmissio n line between the transmitting logic device and the AD9154 . as mentioned in the insertion loss section, minimizing the use of vias, or eliminating them all to gether, reduces one of the primary sources for impedance mismatches on a transmission line. maintain a solid reference beneath (for microstrip) or above and below (for stripline) the differential traces to ensure continuity in the impedance of the transmis sion line. if the stripline technique is used, follow the guidelines listed in the insertion loss section to minimize impedance mismatches and stub effects. another primary source for impedance mismatch is at eithe r end of the transmission line, where care must be taken to match the impedance of the termination to that of the transmission line. the AD9154 handles this internally with a calibrated termination scheme for the receiving end of the line. see the interface power - up and input termination s ection for details on this circuit and the calibration routine. signal skew there are many sources for signal skew, but the two sources to consider when laying out a pcb are interconnect skew within a single jesd204b link and skew between multiple jesd204b links. in each case, keeping the channel lengths matched to within 15 mm is adequate for operating the jesd204b link at speeds of up to 10.6 gbps. managing the interconnect skew within a single link is fairly straightforward. managing multiple links acros s multiple devices is more complex. however, follow the 15 mm guideline for length matching. topology structure the differential serdinx pairs to achieve 50 ? to ground for each half of the pair. stripline vs. microstrip trade - offs are described in the insertion loss section. in either case, it is important to keep these transmission lines separated from potential noise sources such as high speed digital signals and noisy supplies. if using stripline differential traces, route them using a coplanar method, with both traces on the same layer. although this does not offer more noise immunity than the broadside routing method (traces routed on adjacent layers), it is easier to route and manufacture so that the impeda nce continuity is maintained. an illustration of broadside vs. coplanar is shown in figure 86. figure 86 . broadside vs. coplanar differential stripline routing techniques when considerin g the trace width vs. copper weight and thickness, the speed of the interface must be considered. at multigigabit speeds, the skin effect of the conducting material confines the current flow to the surface. maximize the surface area of the conductor by mak ing the trace width made wider to reduce the losses. additionally, loosely couple differential traces to accommodate the wider trace widths. this helps reduce the crosstalk and minimize the impedance mismatch when the traces must separate to accommodate co mponents, vias, connectors, or other routing obstacles. tightly coupled vs. loosely coupled differential traces are shown in figure 87. figure 87 . tightly coupled vs. loosely coupled dif ferential traces ac coupling capacitors the AD9154 requires that the jesd204 b input signals be ac - coupled to the source. these capacitors must be 100 nf and placed as close as possible to the transmitting logic device. to minimize the impedance mismatch at the pads, select the package size of the capacitor so that the pad size on the pcb matches the trace width as closely as possible. layer 1 layer 2 layer 3 layer 4 layer 5 layer 6 layer 7 layer 8 minimize stub effect gnd gnd diff? diff+ y y y add ground vias standard via 1 1389-023 tx diff a tx diff a tx diff b tx active tx diff b tx active broadside differentia l tx lines coplanar differentia l tx lines 1 1389-024 tx diff a tx diff a tx diff b tx diff b tight l y coupled differentia l tx lines loosele y coupled differentia l tx lines 1 1389-025
data sheet AD9154 rev. b | page 83 of 124 syncoutx , sysref, and clk signal s the syncoutx and sysref signals on the AD9154 are low speed lvds differential signals. use controlled impedance trace s routed with 100 ? differential impedance and 50 ? to ground when routing these signals. as with the serdin0 to serdin7 data pairs, it is important to keep these signals separated from potential noise sources such as high speed digital signals and noisy supplies. separate the syncoutx signal from other noisy signals, because noise on the syncoutx might be interpreted as a request for k characters. it is important to keep similar trace lengths for the clk and sysre f signals from the clock source to each of the devices on either end of the jesd204b links, see figure 88 . if using a clock chip that can tightly control the phase of clk and sysref, the trace length matching re quirements are greatly reduced. figure 88 . sysref signal and device clock trace length AD9154 lane 0 lane 1 lane n ? 1 lane n device clock device clock sysref sysref sysref trace length sysref trace length device clock trace length device clock trace length tx device rx device 1 1389-026
AD9154 data sheet rev. b | page 84 of 124 register summary table 92. AD9154 register summary reg . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x000 spi_intfconfa softreset_m lsbfirst_m addrinc_m sdoactive_m sdoactive addrinc lsbfirst softreset 0x00 r/w 0x003 spi_chiptype chiptype 0x04 r 0x004 spi_prodidl prodidl 0x54 r 0x005 spi_prodidh prodidh 0x91 r 0x006 spi_chipgrade prod_grade dev_revision 0x89 r 0x008 dual_page reserved pageindx 0x03 r/w 0x011 pwrcntrl0 pd_bg pddac0 pddac1 pddac2 pddac3 reserved 0xf8 r/w 0x012 txenmask1 dacb_mask daca_mask reserved 0x00 r/w 0x013 pwrcntrl3 reserved ena_pa_ctrl _ from_ paprot_err ena_pa_ctrl _from_ txensm ena_pa_ctrl_ from_blsm ena_pa_ ctrl_from_ spi spi_pa_ ctrl ena_spi_ txen spi_txen 0x20 r/w 0x014 coarse_ group_dly reserved coarse_group_dly 0x88 r/w 0x01f irq_enable0 reserved en_da c plllost en_dac plllock en_ser - plllost en_ser - plllock en_lane - fifoerr reserved 0x00 r/w 0x020 irq_enable1 reserved en_prbsq1 en_prbsi1 en_ prbsq0 en_ prbsi0 0x00 r/w 0x021 irq_enable2 en_paerr0 reserved en_ blnkdone0 en_ refncoclr0 en_ reflock0 en_ re frota0 en_ refwlim0 en_ reftrip0 0x00 r/w 0x022 irq_enable3 en_paerr1 reserved en_ blnkdone1 en_ refncoclr1 en_ reflock1 en_ refrota1 en_ refwlim1 en_ reftrip1 0x00 r/w 0x023 irq_status0 reserved irq_dac - plllost irq_dac - plllock irq_ serplllost irq_ serpl llock irq_lane fifoerr reserved 0x00 r 0x024 irq_status1 reserved irq_prbsq1 irq_prbsi1 irq_ prbsq0 irq_ prbsi0 0x00 r 0x025 irq_status2 irq_paerr0 reserved irq_ blnkdone0 irq_ refncoclr0 irq_ref - lock0 irq_ refrota0 irq_ refwlim0 irq_ reftrip0 0x00 r 0x 026 irq_status3 irq_paerr1 reserved irq_ blnkdone1 irq_ refncoclr1 irq_ reflock1 irq_ refrota1 irq_ refwlim1 irq_ reftrip1 0x00 r 0x030 jesd_checks reserved err_dlyover err_winlimit err_ jesdbad err_ kunsupp err_ subclass err_ intsupp 0x00 r 0x034 sync_ errwindow reserved errwindow 0x00 r/w 0x038 sync_ lasterr_l lasterror_l 0x00 r 0x039 sync_ lasterr_h lastunder lastover reserved last error_h 0x00 r 0x03a sync_ control syncenable syncarm syncclrstky syncclrlast syncmode 0x00 r/w 0x03b sync_status refb usy reserved reflock refrota refwlim reftrip 0x00 r 0x03c sync_ currerr_l currerror_l 0x00 r 0x03d sync_ currerr_h currunder currover reserved curr - error_h 0x00 r 0x040 dac_gain0_i reserved dac_gain_i1 0x03 r/w 0x041 dac_gain1_i dac_gain_i0 0xff r/w 0 x042 dac_gain0_q reserved dac_ gain_q1 0x03 r/w 0x043 dac_gain1_q dac_gain_q0 0xff r/w 0x044 groupdelay comp_i group delay comp i [7:0] 0x00 r/w 0x045 groupdelay comp_q group delay comp q [7:0] 0x00 r/w 0x046 groupdelay comp_byp reserved group - comp_ by pi group - comp_ bypq 0x03 r/w 0x04a mix_mode reserved mix_ mode 0x00 r/w 0x050 nco_clrmode ncoclrarm reserved ncoclrmtch ncoclrpass ncoclrfail reserved ncoclrmode 0x00 r/w 0x051 ncokey_ilsb ncokeyilsb 0x00 r/w 0x052 ncokey_imsb ncokeyimsb 0x00 r/w 0x0 53 ncokey_qlsb ncokeyqlsb 0x00 r/w
data sheet AD9154 rev. b | page 85 of 124 reg . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x054 ncokey_qmsb ncokeyqmsb 0x00 r/w 0x060 pa_thres0 pdp_threshold[7:0] 0x00 r/w 0x061 pa_thres1 reserved pdp_threshold[12:8] 0x00 r/w 0x062 pdp_avg_time pdp_enable pa_bus_ swap reserved pdp_avg_time 0x00 r/w 0x063 pa_power0 pdp_power[7:0] 0x00 r 0x064 pa_power1 reserved pdp_power[12:8] 0x00 r 0x080 clkcfg0 pd_clk01 pd_clk23 pdclockdig pd_pclk pdclock - rec duty_en rf_sync_ en rf_ clkdiv_en 0xfe r/w 0x081 sysref_actrl0 reserved pdsysref hys_on sysref_rise hys_cntrl1 0x10 r/w 0x082 sysref_actrl1 hys_cntrl0 0x00 r/w 0x083 dacpllcntrl synth_ recal reserved enable_ synth reserved 0x00 r/w 0x084 dacpllstatus cp_overrange_h cp_ overrange_l cp_cal_valid vco_cal_ progress reserved rfpll_ lock reserved 0x00 r/w 0x085 dacin teger - word0 bcount 0x06 r/w 0x087 dacloopfilt1 lf_c2_word lf_c1_word 0x88 r/w 0x088 dacloopfilt2 lf_r1_word lf_c3_word 0x88 r/w 0x089 dacloopfilt3 lf_bypass_ r3 lf_bypass_ r1 lf_bypass_c2 lf_bypass_c1 lf_r3_word 0x08 r/w 0x08a daccpcntrl reserved vt_fo rce cp_current 0x20 r/w 0x08b daclogen - cntrl reserved lo_power_mode reserved lodivmode 0x00 r/w 0x08c dacldocntrl1 ldo_ref_sel ldo_bypass_ filt reserved refdivmode 0x00 r/w 0x08d dacldocntrl2 ldo_bypass ldo_inrush ldo_sel ldo_vdrop 0x2b r/w 0x110 data_ format data_fm t reserved 0x00 r/w 0x111 datapath_ ctrl invsinc_ enable reserved dig_gain_ enable phase_adj_ enable modulation_type sel_ sideband i_to_q 0xa0 r/w 0x112 interpmode reserved interpmode 0x01 r/w 0x113 nco_ftw_ update reserved ftw_up - date_ack ftw_up - date_req 0x00 r/w 0x114 ftw0 ftw0 0x00 r/w 0x115 ftw1 ftw1 0x00 r/w 0x116 ftw2 ftw2 0x00 r/w 0x117 ftw3 ftw3 0x00 r/w 0x118 ftw4 ftw4 0x00 r/w 0x119 ftw5 ftw5 0x10 r/w 0x11a nco_phase_ offset0 nco_phase_offset0 0x00 r/w 0x11b nco_phase_ off set1 nco_phase_offset1 0x00 r/w 0x11c nco_phase_ adj0 phaseadj[7:0] 0x00 r/w 0x11d nco_phase_ adj1 phaseadj[12:8] 0x00 r/w 0x11f txen_sm_0 pa_fall pa_rise reserved gp_pa_on_ invert gp_pa_ ctrl txen_sm_ en 0x83 r/w 0x121 txen_sm_2 rise_count_0 0x0f r/w 0 x122 txen_sm_3 rise_count_1 0x00 r/w 0x123 txen_sm_4 fall_count_0 0xff r/w 0x124 txen_sm_5 fall_count_1 0xff r/w 0x12d device_config_ reg0 device_config_0 0x46 r/w 0x12f die_temp_ ctrl0 reserved auxadc_ enable 0x20 r/w 0x132 die_temp0 die_temp_lsb 0x00 r 0x133 die_temp1 die_temp_msb 0x00 r
AD9154 data sheet rev. b | page 86 of 124 reg . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x134 die_temp_ update reserved die_temp _update 0x00 r/w 0x135 dc_offset_ ctrl reserved dc_off - set_on 0x00 r/w 0x136 ipath_dc_ offset_1part0 ipath_dc_offset_1part0 0x00 r/w 0x137 ipath_dc_ offset_1part1 ipath_dc_o ffset_1part1 0x00 r/w 0x138 qpath_dc_ offset_1part0 qpath_dc_offset_1part0 0x00 r/w 0x139 qpath_dc_ offset_1part1 qpath_dc_offset_1part1 0x00 r/w 0x13a ipath_dc_ offset_2part reserved ipath_dc_offset_2part 0x00 r/w 0x13b qpath_dc_ offset_2part reserved qpath_dc_offset_2part 0x00 r/w 0x13c idac_dig_ gain0 idac_dig_gain0 0x00 r/w 0x13d idac_dig_ gain1 reserved idac_dig_gain1 0x08 r/w 0x13e qdac_dig_ gain0 gaincodeq[7:0] 0x00 r/w 0x13f qdac_dig_ gain1 reserved gaincodeq[11:8] 0x08 r/w 0x140 gain_ramp_ up_step0 gain_ramp_up_step0 0x04 r/w 0x141 gain_ramp_ up_step1 reserved gain_ramp_up_step1 0x00 r/w 0x142 gain_ramp_ down_step0 gain_ramp_down_step0 0x09 r/w 0x143 gain_ramp_ down_step1 reserved gain_ramp_down_step1 0x00 r/w 0x146 device_config _reg1 d evice_config1 0x00 r/w 0x147 blsm_stat be_rotate_req reserved 0x00 r/w 0x14b prbs prbs_ good_q prbs_ good_i reserved prbs_ mode prbs_ reset prbs_en 0x10 r/w 0x14c prbs_error_i prbs_count_i 0x00 r 0x14d prbs_error_q prbs_count_q 0x00 r 0x1b0 dacpllt0 v co_pd_in vco_pd_ ptat vco_pd_alc synth_pd ldo_pd reserved logen_ pd reserved 0xfa r/w 0x1b1 dacpllt1 reserved pfd_delay pfd_ edge reserved 0x04 r/w 0x1b2 dacpllt2 ext_alc_ word_en ext_alc_word 0x00 r/w 0x1b3 dacpllt3 ext_band1 0x00 w 0x1b4 dacpllt4 byp _load_ delay vco_cal_offset reserved ext_ band_en ext_ band2 0x78 r/w 0x1b5 dacpllt5 init_alc_value vco_var 0x83 r/w 0x1b6 dacpllt6 reserved poresetb_ vco ext_vco_bitsel vco_lvl_out 0x4a r/w 0x 1b7 dacpllt7 ld_synth reserved cp_ibleed 0x00 r/w 0x1b8 dac pllt8 reserved comp_out cp_cal_ done vco_cal_in_ prog cp_calbits 0x00 r 0x 1b9 dacpllt9 half_vco_ cal_clk dither_ mode machine_ enable cp_offset_ off force_cp_ calbits cap_cal_ en cp_test 0x34 r/w 0x1ba dacpllta machine_state fcp_calbits 0x00 r/w 0x 1bb d acplltb reserved vco_bias_tcf vco_bias_ref 0x0c r/w 0x 1bc dacplltc vco_byp_ biasr reserved vco_comp_ biasr prsc_highr last_ alc _ en prsc_bias _ ctrl 0x00 r/w 0x 1bd dacplltd reserved vco_cal_ ref_mon vco_cal_ref_tcf 0x00 r/w 0x 1be dacpllte reserved vco_pdo_ vr vco_pdo_ vrtcf vco_pdo _caltcf vco_pdo _vcobuf 0x00 r/w 0x 1bf dacplltf i_cal_en i_alc_wait_d i_cal_count fdbck_delay 0x8d r/w
data sheet AD9154 rev. b | page 87 of 124 reg . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x 1c0 dacpllt10 reserved use_new_cal double_f0_ cal_cnt lockdetect_count lock_mode 0x2e r/w 0x1c1 dacpllt11 reserved cp_lvl_ det_pd cp_vl_low cp_vl_high 0x15 r/w 0x1c2 dacpllt15 sdm_bp sdm_pd reserved sdm_prog 0x80 r/w 0x1c3 dacpllt16 reserved sdm_prog3 sdm_prog2 sdm_prog1 0x00 r/w 0x1c4 dacpllt17 reserved vco_var_ref_tcf vco_var_off 0x33 r/w 0x1c5 dacpllt18 reserved vco_var _ref 0x08 r/w 0x200 master_pd reserved spi_pd_ master 0x01 r/w 0x201 phy_pd unusedlanes 0x00 r/w 0x203 generic_pd reserved spi_ sync1_pd spi_ sync2_pd 0x00 r/w 0x206 cdr_reset reserved spi_cdr_ resetn 0x01 r/w 0x230 cdr_ operating_ mode_reg_0 reserved halfrate reserved cdr _ over - samp reserved 0x28 r/w 0x268 eq_bias_reg eq_power_mode reserved 0x62 r/w 0x280 synth_enable_ c ntrl reserved spi_recal_ synth reserved spi_enab - le _synth 0x00 r/w 0x281 pll_status reserved spi_cp_over_ range_high_ rb spi_cp_over _ range_low_r b spi_cp_cal_ valid_rb spi_vco_ cal _in_pro gress _rb spi_cur - rents_ ready_rb spi_pll_ lock_rb 0x00 r 0x284 loop_filter_1 loop_filter_1 0x77 r/w 0x285 loop_filter_2 loop_filter_ 2 0x87 r/w 0x286 loop_filter_3 loop_filter_ 3 0x08 r/w 0x287 cp_cu rrent reserved spi_ serdes_ logen_pow - er_mode spi_cp_current 0x3f r/w 0x289 ref_clk_ divider_ldo reserved spi_ldo_ref _sel spi_ldo_ bypass_filt spi_cdr_oversamp 0x04 r/w 0x28a vco_ldo spi_serdes_ldo_config 0x2b r/w 0x28b pll_pd_reg reserved spi_vco_pd spi_ vco_pd_ ptat spi_vco_pd_ alc spi_syn_pd spi_serdes _ldo_pd spi_serdes_logen_ pd_ core ox7f r/w 0x290 alc_ varactor spi_init_alc_value spi_vco_varactor 0x83 r/w 0x291 vco_output reserved spi_vco_output_level 0x49 r/w 0x294 cp_config spi_half_ vco_cal_ clk sp i_dither_ mode spi_enable_ machine spi_cp_ offset_off spi_cp_ force_ calbits spi_cp_ cal_en spi_cp_test 0xb0 r/w 0x296 vco_bias_1 reserved spi_vco_bias_tcf spi_vco_bias_ref 0x0c r/w 0x297 vco_bias_2 reserved spi_vco_by - pass_bias_ dac_r spi_vco_ comp_by - pas s_biasr spi_pre - scale _ bypass_r spi_last_ alc_en spi_prescale_bias 0x00 r/w 0x299 vco_pd_ overrides reserved spi_vco_pd _override_ var_ref spi_vco_p d_over - ride_var_r ef_tcf spi_vco_ pd_over - ride_cal _tcf spi_vco_ pd_over - ride_vco buf 0x00 r/w 0x29a vco_cal spi _vco_ cal_en spi_vco_cal_alc_wait spi_vco_cal_count spi_fb_clock_adv 0xfe r/w 0x29c cp_level_ detect reserved spi_cp_level _det_pd spi_cp_level_threshold_low spi_cp_level_threshold_high 0x17 r/w 0x29f vco_varactor _control_0 reserved spi_vco_varactor_ref_t cf spi_vco_varactor_offset 0x33 r/w 0x2a0 vco_varactor _ control_1 reserved spi_vco_varactor_ref 0x08 r/w 0x2a7 term_blk1_ctr lreg0 reserved spi_i_tune _r_cal_ termblk1 0x00 r/w 0x2ae term_blk2_ ctrlreg0 reserved spi_i_tune _ r_cal_ termblk2 0x00 r/w 0x300 g eneral_jrx_c trl_0 reserved checksum_ mode reserved duallink current - link enlinks 0x00 r/w 0x301 general_jrx_c trl_1 reserved subclassv_local 0x01 r/w
AD9154 data sheet rev. b | page 88 of 124 reg . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x302 dyn_link_ latency_0 reserved dyn_link_latency_0 0x00 r/w 0x303 dyn_link_ latency_1 reserved dyn_li nk_latency_1 0x00 r/w 0x304 lmfc _ del ay_ 0 reserved lmfcdel0 0x00 r/w 0x305 lmfc _ del ay_ 1 reserved lmfcdel1 0x00 r/w 0x306 lmfcvar 0 reserved lmfcvar0 0x06 r/w 0x307 lmfcvar 1 reserved lmfcvar1 0x06 r/w 0x308 xbar_ln_0_1 reserved xbarval1 xbarval0 0x08 r/w 0x309 xbar_ln_2_3 reserved xbarval3 xbarval2 0x1a r/w 0x30a xbar_ln_4_5 reserved xbarval5 xbarval4 0x2c r/w 0x30b xbar_ln_6_7 reserved xbarval7 xbarval6 0x3e r/w 0x30c fifo_status_ reg_0 lane_fifo_full 0x00 r 0x30d fifo_status_ reg_1 lane_fifo_empty 0x00 r 0x312 syncb_gen_1 reserved syncb_err_dur reserved 0x00 r/w 0x314 spi_sync_ctrl reserved spi_sync_ clk_sel 0x00 r/w 0x315 phy_prbs_ test_en phy_test_en 0x00 r/w 0x316 phy_prbs_ test_ctrl reserved phy_src_err_cnt phy_prbs_pat_sel phy_test _start phy _test _reset 0x00 r/w 0x317 phy_prbs_ test_thres - hold_lobits phy_prbs_threshold_lobits 0x00 r/w 0x318 phy_prbs_ test_thresh - old_midbits phy_prbs_threshold_midbits 0x00 r/w 0x319 phy_prbs_ test_thresh - old_hibits phy_prbs_threshold_hibits 0x00 r/w 0x31a p hy_prbs_ test_errcnt_l obits phy_prbs_err_cnt_lobits 0x00 r 0x31b phy_prbs_ test_errcnt_ midbits phy_prbs_err_cnt_midbits 0x00 r 0x31c phy_prbs_ test_errcnt_h ibits phy_prbs_err_cnt_hibits 0x00 r 0x31d phy_prbs_ test_status phy_prbs_pass 0xff r 0x32c shor t_tpl_ test_0 reserved short_tpl_sp_sel short_tpl_m_sel short_ tpl_test _reset short_ tpl_test_ en 0x00 r/w 0x32d short_tpl_ test_1 short_tpl_ref_sp_lsb 0x00 r/w 0x32e short_tpl_ test_2 short_tpl_ref_sp_msb 0x00 r/w 0x32f short_tpl_ test_3 reserved short_ tpl_fail 0x00 r 0x333 device_ config_reg2 reserved 0x00 r/w 0x334 jesd_bit_ inverse_ctrl invlanes 0x00 r/w 0x400 did_reg did_rd 0x00 r 0x401 bid_reg adjcnt_rd bid_rd 0x00 r 0x402 lid0_reg reserved adjdir_rd phadj_rd lid0_rd 0x00 r 0x403 scr_l_reg sc r_rd reserved l_rd 0x00 r 0x404 f_reg f_rd 0x00 r 0x405 k_reg reserved k_rd 0x00 r 0x406 m_reg m_rd 0x00 r 0x407 cs_n_reg cs_rd reserved n_rd 0x00 r 0x408 np_reg subclassv_rd np_rd 0x00 r
data sheet AD9154 rev. b | page 89 of 124 reg . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x409 s_reg jesdv_rd s_rd 0x00 r 0x40a hd_cf_reg hd_rd reserv ed cf_rd 0x00 r 0x40b res1_reg res1_rd 0x00 r 0x40c res2_reg res2_rd 0x00 r 0x40d checksum_reg lane0checksum_rd 0x00 r 0x40e compsum0_reg fcmp0_rd 0x00 r 0x412 lid1_reg reserved lid1_rd 0x00 r 0x415 checksum1_ reg fchk1_rd 0x00 r 0x416 compsum1_reg fcmp1_rd 0x00 r 0x41a lid2_reg reserved lid2_rd 0x00 r 0x41d checksum2_ reg fchk2_rd 0x00 r 0x41e compsum2_ reg fcmp2_rd 0x00 r 0x422 lid3_reg reserved lid3_rd 0x00 r 0x425 checksum3_ reg fchk3_rd 0x00 r 0x426 compsum3_ reg fcmp3_rd 0x00 r 0x42a lid 4_reg reserved lid4_rd 0x00 r 0x42d checksum4_ reg fchk4_rd 0x00 r 0x42e compsum4_ reg fcmp4_rd 0x00 r 0x432 lid5_reg reserved lid5_rd 0x00 r 0x435 checksum5_ reg fchk5_rd 0x00 r 0x436 compsum5_ reg fcmp5_rd 0x00 r 0x43a lid6_reg reserved lid6_rd 0x0 0 r 0x43d checksum6_ reg fchk6_rd 0x00 r 0x43e compsum6_ reg fcmp6_rd 0x00 r 0x442 lid7_reg reserved lid7_rd 0x00 r 0x445 checksum7_ reg fchk7_rd 0x00 r 0x446 compsum7_ reg fcmp7_rd 0x00 r 0x450 ils_did did 0x00 r/w 0x451 ils_bid adjcnt bid 0x00 r/w 0x452 ils_lid0 reserved adjdir phadj lid0 0x00 r/w 0x453 ils_scr_l scr reserved l 0x83 r/w 0x454 ils_f f 0x00 r/w 0x455 ils_k reserved k 0x1f r/w 0x456 ils_m m 0x01 r 0x457 ils_cs_n cs reserved n 0x1f r/w 0x458 ils_np subclassv np 0x2f r/w 0x459 i ls_s jesdver s 0x20 r/w 0x45a ils_hd_cf hd reserved cf 0x80 r/w 0x45d ils_checksum lane0checksum 0x45 r/w 0x46b errcntrmon err cntr mon 0x00 r/w 0x46c lanedeskew lanedeskew 0x0f r/w 0x46d baddisparity baddis parity 0x00 r/w 0x46e nitdisparity nitd is pari ty 0x00 r/w 0x46f unexpectedk - char uekc 0x00 r/w 0x470 codegrpsync - flg codegrpsync 0x00 r/w 0x471 framesyncflg framesync 0x00 r/w
AD9154 data sheet rev. b | page 90 of 124 reg . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x472 goodchksum - flg goodchecksum 0x00 r/w 0x473 initlanesync - flg initiallanesync 0x00 r/w 0x476 ctrlreg1 f_again 0x01 r /w 0x477 ctrlreg2 ilas_mode reserved threshold_ mask_en reserved 0x00 r/w 0x478 kval ksync 0x01 r/w 0x47a irqvector baddis_ mask nitd_mask uekc_mask reserved initiallane - sync_mask badcheck - sum_mask reserved c odegrp sync_ mask 0x00 r/w 0x47b syncassertion - mask baddis_s nit_s ucc_s cmm cmm_enable reserved 0x08 r/w 0x47c errorthres eth 0xff r/w 0x47d laneenable lane_ena 0x0f r/w 0x47e ramp_ena reserved e na_ ramp_ check 0x00 r/w 0x520 dig_test0 reserved dc_test_ mod reserved 0x1c r/w 0x521 test_dc_ valuei 0 test_dc_valuei0 0x00 r/w 0x522 test_dc_ valuei1 test_dc_valuei1 0x00 r/w 0x523 test_dc_ valueq0 test_dc_valueq0 0x00 r/w 0x524 test_dc_ valueq1 test_dc_valueq1 0x00 r/w
data sheet AD9154 rev. b | page 91 of 124 register details table 93. AD9154 register details addr. name bits bit name settings description reset access 0 x 000 spi_intfconfa 7 softreset_m soft reset (mirror) . 0 x 0 r 6 lsbfirst_m lsb first (mirror) . 0 x 0 r 5 addrinc_m addr ess inc re ment (mirror) . 0 x 0 r 4 sdoactive_m sdo active (mirror) . 0 x 0 r 3 sdoactive sdo active . 0 x 0 r/w 2 addrinc addr ess inc rement. when set , causes i ncrementing streaming addresses; otherwise , descending addresses are generated. 0 x 0 r/w 1 streaming addresses are incremented . 0 streaming addresses are decr e mented . 1 lsbfirst lsb first. when set , causes input and output data to be oriented lsb first. if this bit is clear, data is oriented msb first. 0 x 0 r/w 1 shift lsb in first . 0 shift msb in first . 0 softreset soft reset. setting this bit init iates a reset. this bit is auto clearing after the soft reset is complete. 0 x 0 r/w 1 pulse the soft reset l ine . 0 release soft reset . 0 x 003 spi_chiptype [7:0] chiptype high speed dac . 0 x 4 r 0 x 004 spi_prodidl [7:0] prodidl product id low . 0 x 54 r 0 x 005 spi_prodidh [7:0] prodidh product id high . 0 x 91 r 0 x 006 spi_chip - grade [7:4] prod_grade product grade . 0x 8 r [3:0] dev_revision device revision . 0x 9 r 0 x 008 dual_page [7:2] reserved reserved. 0 x 0 r [1:0] pageindx page or index pointer . 0 x 3 r/w 1 select link a . 2 select link b . 3 select link a and link b . 0x011 pwrcntrl0 7 pd_bg reference power - down . 0 x 1 r/w 0 reference on . 1 reference powered down. overrides txenx masked bit. 6 pddac 0 pd i channel dac 0. 0 x 1 r/w 0 enable dac0 i channel dual0 . 1 power down d ac0 i channel dual0. overrides txenx masked bit . 5 pddac 1 pd q c hannel dac 1 . 0 x 1 r/w 0 enable q channel dac of dual a . 1 power down q channel dac of dual a . overrides txenx masked bit. 4 pddac 2 pd i channel dac 2 . 0 x 1 r/w 0 enable i channel dac of dual b . 1 power down i channel dac of dual b . overrides txenx masked bit. 3 pddac 3 pd q c hannel dac 3 . 0 x 1 r/w 0 enable q channel dac of dual b . 1 powe rs down q channe l dac of dual b . overrides txenx masked bit. [ 2:0 ] reserved reserved. 0 x 0 r
AD9154 data sheet rev. b | page 92 of 124 addr. name bits bit name settings description reset access 0 x 012 txenmask 1 7 dacb_mask dual 23 dac p ower - down m ask for txen 1 . 0 x 0 r/w 0 default power - down to control by power - down bit only. 1 if txen 1 is low , dac 2 and dac 3 are powered down; otherwise state of indiv i dual power - downs . 6 daca_mask dual 01 dac power - down mask fo r txen0 . 0 x 0 r/w 0 default power - down to control by power - down bit only . 1 if txen0 is low , dac 0 an d dac 1 are powered down; otherwise state of indiv i dual power - downs . [ 5 :0] reserved reserved 0 x 0 r/w 0 x 013 pwrcntrl 3 7 reserved reserved. 0 x 0 r 6 ena_pa_ctrl_ from_paprot_ err control pa enable from paprot block . 0 x 0 r/w 5 ena_pa_ ctrl_ from_txensm control pa enable from txen state machine . 0 x 1 r/w 4 ena_pa_ctrl_ from_blsm contro l pa enable from b lanking state machine . 0 x 0 r/w 3 ena_pa_ctrl_ from_spi control pa enable via spi. 0 x 0 r/w 2 spi_pa_ctrl pa on/off v ia spi . 0 x 0 r/w 1 ena_spi_txen txen x from spi control . 0 x 0 r/w 0 spi_txen spi txen x . 0 x 0 r/w 1 txen x spi is high . 0 txen x spi is low . 0 x 014 coarse_ group_dly [ 7:4 ] reserved reserved. 0 x 0 r [ 3:0 ] coarse_ group_ dly coarse group dela y. the range of the delay is ? 4 to + 3 dac clock periods and the resolution is 1/2 dac clock period. 0 x 8 r/w 0 minimum delay . 15 maximu m delay. 0 x 01f irq_enable 0 [ 7 :6] reserved reserved . 0x0 r/w 5 en_dacplllost enable dac pll lost detection. the dacplllock , when enabled, show s that the dac (clock g eneration) pll has dropped its lock state. 0 x 0 r/w 1 enable dac pll lost . 4 en_dacplllock enable dac pll lock detection. the dacplllock , when enable d , show s that the dac (clock g eneration) pll has reached a lock state. 0 x 0 r/w 1 enable dac pll lock . 3 en_serplllost enable serdes pll lost detection. the serplllock , when enabled , show s that the serdes ( jesd 204b interface) pll has dro pped its lock state. 0 x 0 r/w 1 enable serdes pll lost . 2 en_serplllock enable serdes pll lock detection. the serplllock , when enabled , show s that the serdes (jesd 204b interface) pll has reached a lock state. 0 x 0 r/w 1 enable se rdes pll lock .
data sheet AD9154 rev. b | page 93 of 124 addr. name bits bit name settings description reset access 1 en_lanefifoerr enable lane fifo error detection. a l ane fifo error occurs when there is a full or empty condition on any of th e fifo s between the deserializer block and the core digital. an error on this fifo requires a link dis able and re - enable to remove. the status of the lane fifos can be found in register 0x30c (fifo full) and register 0x30d (fifo empty). 0 x 0 r/w 1 enable lane fifo error . 0 reserved reserved 0 x 0 r/w 0 x 020 irq_enable 1 [ 7 : 4 ] reserved res erved. 0 x 0 r 3 en_prbsq 1 e nable prbs imaginary dac dual b interrupt . 0 x 0 r/w 1 enable prbs q1 . 2 en_prbsi 1 enable prbs real dac dual b interrupt . 0 x 0 r/w 1 enable prbs i1 . 1 en_prbsq 0 enable prbs imaginary dac dual a interrupt . 0 x 0 r/w 1 enable prbs q0 . 0 en_prbsi 0 enable prbs real dac dual a interrupt . 0 x 0 r/w 1 enable prbs i0 . 0 x 021 irq_enable 2 7 en_paerr0 link a pa error . 0 x 0 r/w 1 enable pa error . 6 rese rved reserved . 0 x 0 r/w 5 en_blnkdone0 link a blanking done . 0 x 0 r/w 1 enable link a blanking done . 4 en_refncoclr0 link a nco clear tripped . 0 x 0 r/w 1 nco clear tripped . 3 en_reflock0 link a alignment locked . 0 x 0 r/w 1 enable ref locked interrupt . 2 en_refrota0 link a alignment rotate . 0 x 0 r/w 1 enable ref rotate interrupt . 1 en_refwlim0 link a over/under threshold . 0 x 0 r/w 1 enable over/under limit interrupt . 0 en_reftrip0 link a alignment trip . 0 x 0 r/w 1 enable ref tripped interrupt . 0 x 022 irq_enable3 7 en_paerr1 link b pa error . 0 x 0 r/w 1 enable pa error . 6 reserved reserved . 0 x 0 r/w 5 en_blnkdone1 link b b lanking done . 0 x 0 r/w 1 enable link b blanking done . 4 en_refncoclr1 link b nco clear tripped . 0 x 0 r/w 1 nco clear tripped . 3 en_reflock1 link b alignment locked . 0 x 0 r/w 1 enable ref locked interrupt . 2 en_refrota1 link b alignment rotate . 0 x 0 r/w 1 enable ref rotate interrupt . 1 en_refwlim1 link b over/under threshold . 0 x 0 r/w 1 enable over/under limit interrupt . 0 en_reftrip1 link b alignment trip . 0 x 0 r/w 1 enable ref tripped interrupt . 0 x 023 irq_status 0 [ 7:6 ] reserved reserved. 0 x 0 r 5 irq_dacplllost dac pll lost . 0 x 0 r 1 dac pll lost . 4 irq_dacplllock dac pll lock . 0 x 0 r 1 dac pll lock .
AD9154 data sheet rev. b | page 94 of 124 addr. name bits bit name settings description reset access 3 irq_s erplllost serdes pll lost . 0 x 0 r 1 serdes pll lost . 2 irq_serplllock serdes pll lock . 0 x 0 r 1 serdes pll lock . 1 irq_lanefifoerr lane fifo error . 0 x 0 r 1 lane fifo error . 0 reserved reserved 0 x 0 r 0 x 024 irq_status 1 [ 7 : 4 ] reserved reserved. 0 x 0 r 3 irq_prbsq 1 prbs data check error dac b imag inary. 0 x 0 r 1 service prbs q1 . 2 irq_prbsi 1 prbs data check error dac b real . 0 x 0 r 1 service prbs i1 . 1 irq_pr bsq 0 prbs data check error dac a imag inary. 0 x 0 r 1 service prbs q0 . 0 irq_prbsi 0 prbs data check error dac a real . 0 x 0 r 1 service prbs i0 . 0 x 025 irq_status 2 7 irq_paerr0 link a pa error . 0 x 0 r 1 service link a pa error . 6 reserved reserved . 0 x 0 r 5 irq_blnkdone0 link a blanking done . 0 x 0 r 1 link a blank done . 4 irq_refncoclr0 link a alignment underr ange . 0 x 0 r 1 nco clear tripped . 3 irq_reflock0 link a bist done . 0 x 0 r 1 link a alignment locked . 2 irq_refrota0 link a alignment trip . 0 x 0 r 1 rotate interrupt occurred. 1 irq_refwlim0 link a alignment lock . 0 x 0 r 1 service over/under limit interrupt . 0 irq_reftrip0 link a alignment rotate . 0 x 0 r 1 trip interrupt occurred . 0 x 026 irq_status 3 7 irq_paerr1 link b pa error . 0 x 0 r 1 service link b pa error . 6 reserved reserved . 0 x 0 r 5 irq_blnkdone1 reserved 0x0 r 4 irq_refncoclr1 link b alignment underr ange . 0 x 0 r 1 nco clear tripped . 3 irq_reflock1 link b bist done . 0 x 0 r 1 link b alignment locked . 2 irq_refrota1 link b alignment trip . 0 x 0 r 1 rotate inter rupt occurred. 1 irq_refwlim1 link b alignment lock . 0 x 0 r 1 service over/under limit interrupt . 0 irq_reftrip1 link b alignment rotate . 0 x 0 r 1 ref trip . 0 x 030 jesd_checks [ 7:6 ] reserved reserved. 0 x 0 r 5 err_dlyover lmfc_delay > jesd_k parameter . 0 x 0 r 1 lmfc_delay > jesd_k . 4 err_winlimit unsupported win dow limit . 0 x 0 r 1 unsupported win dow limit . 3 err_jesdbad unsupported m/l/s/f selection . 0 x 0 r 1 thi s jesd combination is not supported .
data sheet AD9154 rev. b | page 95 of 124 addr. name bits bit name settings description reset access 2 err_kunsupp unsupported k values . 0 x 0 r 1 k value unsupported . 1 err_subclass unsupported subclassv value . 0 x 0 r 1 unsupported subclass value . 0 err_intsupp unsupport ed interpolation factor . 0 x 0 r 1 error with interpolation value . 0 x 034 sync_ errwindow [7:3] reserved reserved . 0 x 0 r [2:0] errwindow sync error window. synchronization rotates the clock based on a difference in the sample of the cur rent phase of the internal clocks and the programmed target based o n the sy sref sample time. if sysref can not be guaranteed to always exist in the same period of the device clock associated with the target phase from sysref to sysref (errwindow = 0) , t hen the user may choose to apply an error window to synchronization . the error window allow s the sysref sample phase to vary within the confines of the window without triggering a clock adjustment. 0 x 0 r/w 0 error window tolerance 1/2 . 1 error window tolerance 1 . 2 error window tol erance 2 . 3 error window tolerance 3 . 4 error window tolerance 4 . 5 error window tolerance 5 . 6 error window tolerance 6 . 7 error window tolerance 7 . 0 x 038 sync_ lasterr_l [7:0] lasterror_l sy nc last error[7:0]. the value of sync_lasterr_l and sync_lasterr_h[0] for the readback sync_lasterr. sync_lasterr is a measure of the error between the s ysref sample phase and the target value that caused the last clock adjustment. this value is sticky and does not update until a clock adjustment occurs. clear t his value using the syncclrlast bit. the v alue is in dac clocks. 0 x 0 r 0 x 039 sync_ lasterr_h 7 lastunder sync last error under flag. this bit shows that the phase error between the sysref sample point and the target is below the error window limit. 0 x 0 r 1 current phase error over window tolerance . 6 lastover sync last error over flag. this bit shows that the phase error between the sysref sample point and the target i s above the error window limit. 0 x 0 r 1 last phase error under window tolerance . [5:1] reserved reserved. 0 x 0 r 0 lasterror_h sync last error, bit 8, and flags . 0 x 0 r 0 x 03a sync_ control 7 syncenable sync logic enable . 0 x 0 r/w 1 enable sync logic . 0 disable sync logic . 6 syncarm sync arming strobe . 0 x 0 r/w 1 sync one - shot arming . 5 syncclrstky sync sticky bit clear . 0 x 0 r/w 1 clear sticky status bits refrota and reftrip . 4 syncclrlast sync clear last . 0 x 0 r/w 1 clear the last errors .
AD9154 data sheet rev. b | page 96 of 124 addr. name bits bit name settings description reset access [3:0] syncmode sync mode . 0 x 0 r/w 0 reserved . 1 sync one - shot mode . 2 sync continuous mode . 5 reserved . 6 reserved . 8 sync monitor only mode . a sync one - shot then monitor . 9 sync one - shot then monitor . d reserved .. e reserved 0x03b sync_status 7 refbusy sync machine busy . 0 x 0 r 1 sync logic sm is busy . [6:4] reserved reserved. 0 x 0 r 3 reflock sync alignment locked . 0 x 0 r 1 sync lo gic aligned within window . 2 refrota sync rotated . 0 x 0 r 1 sync logic rotated with sysref ( sticky ) . 1 refwlim sync alignment limit range . 0 x 0 r 1 phase e rror outside of specified window error threshold. 0 reftrip sync tripped after arming . 0 x 0 r 1 sync received sysref pulse ( sticky ) . 0 x 03c sync_ currerr_l [7:0] currerror_l sync alignment error . this register gives the user real time access of the sysref to the internal clock counters. the value of sync_currerr = (sync_currerr_h[0],sync_currerr_l) is the difference between the sysref position relative to the clock divider and the target position relative to the internal counter. this register monitor s the phase of the internal clocks in monitor modes of operation. if an adjustment of the clocks is made on any given sysref , the value of the phase error is placed into sync_lasterr and sync_currerr is forced to 0 . 0 x 0 r 0 x 03d sync_ currerr_h 7 currunder sync current error under flag. 0 x 0 r 1 current phase error under window tolerance . 6 currover sync current error over flag. 0 x 0 r 1 current phase error over window tolerance . [5:1] reserved reserved. 0 x 0 r 0 currerror_h sync current error[8] . 0 x 0 r 0 x 040 dac_gain0_i [7:2] reserved reserved. 0 x 0 r [1:0] dac_gain_i1 i dac current scaling msbs 0x 3 r/w 0 x 041 dac_gain1_i [7:0] dac_gain_i0 i dac current scaling lsbs . 0x ff r/w 0 x 042 dac_gain0_q [7:2] reserved reserved. 0 x 0 r [1:0] dac_gain_q1 q dac current scaling msbs . 0x 3 r/w 0 x 043 dac_gain1_ q [7:0] dac_gain_q0 q dac current scaling lsbs . 0x ff r/w 0 x 044 groupdelay comp_i [7:0] group delay comp i [7:0] group delay compensation bits for i channel . these bits set the gro up delay compensation for the i channel dac. 0 x 0 r/w 0 x 045 groupdelay comp_q [7:0] group delay comp q [7:0] group delay compensation bits for q channel . these bits set the group delay compensation for the q channel dac. 0 x 0 r/w 0 x 046 groupdelay comp_byp [7:2] reserved reserved. 0 x 0 r
data sheet AD9154 rev. b | page 97 of 124 addr. name bits bit name settings description reset access 1 groupcomp_ bypi bypass the q channel group delay compensation circuitry . 0 x 1 r/w 0 groupcomp_ bypq bypass the i channel group delay compensation circuitry . 0 x 1 r/w 0 x 04a mix_mode [7:1] reserved reserved. 0 x 0 r 0 mix_mode mix mode enable . 0 x 0 r/w 0 mix mode off . 1 mix mode on . 0 x 050 nco_ clrmode 7 ncoclrarm arm nco clear. arms nco clearing operation . 0 x 0 r/w 1 arm nco clear logic . 6 reserved reserved. 0 x 0 r 5 ncoclrmtch nco clear data match . 0 x 0 r 1 key nco clear data match . 4 ncoclrpass nco clear pass ed . 0 x 0 r 1 nco clear took effect . 3 ncoclrfail nco clear failed . 0 x 0 r 1 nco res et during rotate . 2 reserved reserved. 0 x 0 r [1:0] ncoclrmode nco cl ear mode . 0 x 0 r/w 0 nco clearing disabled . 2 nco clear on data key . 1 nco clear on sysref . 0 x 051 ncokey_ilsb [7:0] ncokeyilsb nco datakey for i channel lsb . 0 x 0 r/w 0 x 052 ncokey_imsb [7:0] ncokeyimsb nco datakey f or i channel msb . 0 x 0 r/w 0 x 053 ncokey_qlsb [7:0] ncokeyqlsb nco datakey for q channel lsb . 0 x 0 r/w 0 x 054 ncokey_ qmsb [7:0] ncokeyqmsb nco datakey for q channel msb . 0 x 0 r/w 0 x 060 pa_thres0 [7:0] pdp_threshold [7:0] average power threshold for co mparison . 0 x 0 r/w 0 x 061 pa_thres1 [7:5] reserved reserved. 0 x 0 r [4:0] pa_threshold_ msb average power threshold for comparison . 0 x 0 r/w 0 x 062 pdp_avg_time 7 pdp_enable 1 enable average power calculation and error detection 0 x 0 r/w 6 pa_bu s_swap swap channel a or channel b data bus for power calculation . 0 x 0 r/w [5:4] reserved reserved. 0 x 0 r [3:0] pdp_avg_time set power average time . 0 x 0 r/w 0 x 063 pa_power0 [7:0] pdp_power[7:0] average power bus = i 2 + q 2 (i/q use 6 msbs of data bus ) . 0 x 0 r 0 x 064 pa_power1 [7:5] reserved reserved. 0 x 0 r [4:0] pdp_power[12:8] average power bus = i 2 + q 2 (i/q use 6 msbs of data bus ) . 0 x 0 r 0 x 080 clkcfg0 7 pd_clk01 power - down clock for dual a . 0 x 1 r/w 0 enable clock div ider in dual a . 1 disable clock divider in dual a . 6 pd_clk23 power - down clock for dual b . 0 x 1 r/w 0 enable clock divider in dual b . 1 power - down clock divider in dual b . 5 pdclock dig power - down clock s to all dacs . 0 x 1 r/w 0 enable clock for all dacs . 1 power - down clock for all dacs .
AD9154 data sheet rev. b | page 98 of 124 addr. name bits bit name settings description reset access 4 pd_pclk power - down cal ibration reference / serdes pll clock . 0 x 1 r/w 0 enable clock to serdes pll/ cal ibration logic . 1 disable clock to serdes pll/ cal ibration logic . 3 pdclock rec power - down clock receiver . 0 x 1 r/w 0 enable clock receiver analog buffer . 1 power - down clock receiver analog buffer . 2 duty_en enable duty cycle control of clock receiver , always = 1 . 0 x 1 r/w 1 rf_sync_en enable sysref timing for rf clock chain . 0 x 1 r/w 0 rf_clkdiv_en enable rf cloc k divider. the rf clock divider divide s the input clock by 2 and provide s the result to the dac for sampling. 0 x 0 r/w 0 rf clock divider disabled . 1 rf clock divider enabled . 0 x 081 sysref_ actrl0 [7:5] reserved reserved. 0 x 0 r 4 pdsysref power down sysref buffer. this bit powers down the sysref receiver. for s ubclass 1 operation to work, this buffer must be enabled. 0 x 1 r/w 3 hys_on hysteresis on. this bit enables the programmable hysteresis control for the sysref receiver. 0 x 0 r/w 0 disable hysteresis in sysref receiver . 1 enable hysteresis in sysre f receiver . 2 sysref_rise use sysref rising edge . 0 x 0 r/w 0 use sysref falling edge for alignment . 1 use sysref rising edge for alignment . [1:0] hys_cntrl1 msbs of hysteresis contr ol. hysteresis control bits a re control bits for the amount of hysteresis in the sysref receiver. each of the ten bits adds 10 mv of differential hys teresis to the receiver input. two of the 10 bits are contained here. the other 8 bits are in hys_cntrl0. 0 x 0 r/w 0 x 082 sysref_ actrl1 [7:0] hys_cntrl0 low bits of hysteresis control . hysteresis control bits are control bits for the amount of hysteresis in the sysref receiver. each of the ten bits adds 10 mv of differential hys teresis to the receiver input. eight of the 10 bits are co ntained here. the other 2 bits are in hys_cntrl1. 0 x 0 r/w 0 x 083 dacpllcntrl 7 synth_recal recalibra te vco band. set this bit to re initialize the calibration of the vco band in the dac pll. this bit does not power cycle the dac pll, nor does i t recalibra te the charge pump. set t his bit after changing any setting associated with the pll. do not set this bit until after an initial pll lock is achieved. 0 x 0 r/w [6:5] reserved reserved. 0 x 0 r
data sheet AD9154 rev. b | page 99 of 124 addr. name bits bit name settings description reset access 4 enable_synth synthesizer enable. the bit initiates the start - up sequence of the dac pll. the start - up sequence is as follows: 0 x 0 r/w 1. enable the bias currents . 2. enable dac ldo . 3. wait for ldo to settle . 4. calibrate dac pll charge pump (the dac charge pump will only cali brate upon the first setting of enable_synth) . 5. calibrate the band of the pll . 6 . settle and lock. 0 disable synthesizer including all currents and calibration codes . 1 power up synthesizer and initiate calibration sequence. [3:0] reserved reserved. 0 x 0 r 0 x 084 dacpll - status 7 cp_ overrange_h charge pump high overrange. this bit indicates that the charge pump voltage is too high and a recalibration must be applied. 0 x 0 r 0 control voltage not too high . 1 control voltage too h igh . 6 cp_ overrange_l charge pump low overrange. this bit indicates that the charge pump voltage is too low and a recalibration must be applied. 0 x 0 r 0 control voltage not too low . 1 control vo ltage too low . 5 cp_cal_valid charge pump cal ibration valid. this bit indicates that the charge pump has been successfully calibrated. the selection as to whether the charge pump needs to be calibrated u pon startup can be found i n register 0 x 1 b 9 . 0 x 0 r 0 if cp_cal_en low, this stays low. 1 if cp_cal_en high (def ), this hap pens when charge pump is calibr ated . 4 vco_cal_ progress vco calibration in progress. this bit is high if the vco calibration is currently occurring . if this bit is high for more than 1 s ec there is something wrong with the vco calibration. 0 x 0 r 0 vco not calibrating . 1 vco calibrating . [3:2] reserved reserved. 0 x 0 r 1 rfpll_lock pll lock bit . this bit is set high by the pll once the pll has achieved lock for the count set by lock_mode bits in register 0 x 1 c 0 . 0 x 0 r 1 pll locked . 0 pll unlocked . 0 reserved reserved. 0 x 0 r 0 x 085 dacinteger word0 [7:0] bcount bi ts[7:0] of the integer tuning wor d. this bit controls the integer feedback divider for the dac pll. the frequency of the dac clock can be determined by the following equations : 0 x 6 r/w f dac = f ref /( refdivmode ) 2 bcount f vco = f ref /( refd ivmode ) 2 bcount lodivmode the m inimum value is 6 .
AD9154 data sheet rev. b | page 100 of 124 addr. name bits bit name settings description reset access 0 x 087 dacloopfilt1 [7:4] lf_c2_word c2 control word . 0 x 8 r/w [3:0] lf_c1_word c1 control word . 0 x 8 r/w 0 x 088 dacloopfilt2 [7:4] lf_r1_word r1 control word . 0 x 8 r/w [3:0] lf_c3_word c3 c ontrol word . 0 x 8 r/w 0 x 089 dacloopfilt3 7 lf_bypass_r3 bypass r3 res istor. 0 x 0 r/w 0 enable r3 res istor programming start at 0 . 1 disable r3 res istor is lf_r3_word = 0 . 6 lf_bypass_r1 bypass r1 res istor. 0 x 0 r/w 0 enable r1 resistor programming at 0 . 1 disable r1 if lf_r1_word = 0 . 5 lf_bypass_c2 bypass c2 cap acitor. 0 x 0 r/w 0 enable c2 cap acitor programming at 0 . 1 disable c2 cap acitor is lf_c2_word = 0 . 4 lf_bypass_c1 bypass c1 cap acitor. 0 x 0 r/w 0 enable c1 cap acitor programming at 0 . 1 disable c1 cap acitor if lf_c1_word = 0 . [3:0] lf_r3_word r3 control word . 0 x 8 r/w 0 x 08a daccpcntrl 7 reserved reserved. 0x 0 r 6 vt_force vt control out . 0 x 0 r/w 0 control voltage not brought out for test . 1 control voltage brought out for test . [5:0] cp_current charge pump current control . 0 x 20 r/w 0 x 08b daclogen cntrl [7:6] reserved reserved. 0 x 0 r [5:4] lo_power_ mode local oscillator generator ( logen ) power mod e . 0 x 0 r/w 0 fu l l power vco, 8 ghz to 12 gh z . 1 half power vco, 6 ghz to 8 ghz . 3 off . [3:2] reserved reserved. 0 x 0 r [ 1:0] lodivmode logen division . 0 x 0 r/w 0 reserved . 1 divide by 4 vco to dac clock . 2 divide by 8 vco to dac clock . 3 divide by 16 vco to dac clock . 0 x 08c dac - ldocntrl1 7 ldo_ref_sel reference selection bit . 0 x 0 r/w 0 generate reference from bg . 1 generate reference from supply . 6 ldo_bypass_ f i lt disable ldo voltage filter . 0 x 0 r/w 0 enable voltage filter to ldo input . 1 disable voltage filter to ldo i nput . [5:3] reserved reserved. 0 x 0 r [2:0] refdivmode reference clock division ratio . 0 x 0 r/w 0 1 . 1 2 . 2 4 . 3 8 . 4 16 . 5 32 . 6 16 . 7 32 .
data sheet AD9154 rev. b | page 101 of 124 addr. name bits bit name settings description reset access 0 x 08d dac - ldocntrl2 7 ldo_bypass bypass ldo function . 0 x 0 r/w 0 ldo operates normally . 1 ldo output shorted to vdd . [6:5] ldo_inrush ldo startup speed control . 0 x 1 r/w [4:2] ldo_sel ldo voltage and power setu p . 0 x 2 r/w 0 1.08 v low power . 1 1.08 v mid power . 2 1.08 v high power . 3 not used . 4 1.02 v low power . 5 1.02 v mid power . 6 1.02 v high power . 7 not used . [1:0] ldo_vdrop ldo passgate control . 0 x 3 r/w 0 one pass gate used . 1 two pass gates used . 2 three pass gates used . 3 four pass gates used . 0 x 110 data_format 7 binary_ fmt binary or twos complementary for mat on data bus . 0 x 0 r/w 0 input data is two s compliment . 1 input data is offset binary . [6:0] reserved reserved. 0 x 0 r 0 x 111 datapath_ ctrl 7 invsinc_enable 1 enable inver se sinc filter . 0 x 1 r/w 6 reserved reserved . 0 x 0 r 5 dig_gain_ enable 1 enable digital gain . 0 x 1 r/w 4 phase_adj_ enable 1 enable phase compensation . 0 x 0 r/w [3:2] modulation_ type selects type of modulation operation . 0 x 0 r/w 0 no modulation . 1 fine modulati on (uses ftw) . 2 f s /4 modulation . 3 f s /8 modulation . 1 sel_sideband 1 select upper or lower sideband from modulation result . 0 x 0 r/w 0 i_to_q 1 send i datapath into q dac. 0 x 0 r/w 0 x 112 interpmode [7:3] reserved reserved. 0 x 0 r [2:0] interpmode interpolation mode. 0 x 1 r/w 0 1x (bypass) . 1 2x mode . 3 4x mode . 4 8x mode . 0 x 113 nco_ftw_ update [7:2] reserved reserved. 0 x 0 r 1 ftw_update_ ack frequency tuning word update acknowledge . 0 x 0 r 0 ftw_update_ req frequency tuning word update request from spi . 0 x 0 r/w 0 x 114 ftw 0 [ 7:0 ] ftw 0 nco frequency tuning word , ftw[7:0] . 0 x 0 r/w 0 x 115 ftw 1 [ 7:0 ] ftw 1 nco frequency tuning word , ftw[15:8] . 0 x 0 r/w 0 x 116 ftw 2 [ 7:0 ] ftw 2 nco frequency tuning word , ftw[23:16] . 0 x 0 r/w
AD9154 data sheet rev. b | page 102 of 124 addr. name bits bit name settings description reset access 0 x 117 ftw3 [7:0] ftw3 nco frequency tuning wor d, ftw[31:24] . 0 x 0 r/w 0 x 118 ftw4 [7:0] ftw4 nco frequency tuning word , ftw[39:32] . 0 x 0 r/w 0 x 119 ftw5 [7:0] ftw5 nco frequen cy tuning word , ftw[47:40] . 0 x 10 r/w 0 x 11a nco_phase_ offset0 [7:0] nco_phase_ offset0 nco phase offset , nco_phase_offset[7:0] . 0 x 0 r/w 0 x 11b nco_phase_ offset1 [7:0] nco_phase_ offset1 nco phase offset , nco_phase_offset[15:8] . 0 x 0 r/w 0 x 11 c nco_ ph aseadj[7:0] [7:0] phaseadj[7:0] phase compensation word, phase_adj[7:0] . 0 x 0 r/w 0 x 11d nco_ phaseadj [12:8] [7:0] phaseadj[12:8] phase compensation word , phase_adj[12:8] . 0 x 0 r/w 0 x 11f txen_sm_0 [7:6] pa_fall pa fall control . 0 x 2 r/w [5:4] pa_ rise pa rises control . 0 x 0 r/w 3 reserved reserved. 0 x 0 r 2 gp_pa_on_ invert external modulator polarity invert . 0 x 0 r/w 1 gp_pa_ctrl external pa control . enabled by default to allow e xternal mod control instead of s ync signal throug h this pin . 0 x 1 r/w 0 txen_sm_en enable txen state machine . 0 x 1 r/w 0 x 121 txen_sm_ 2 [ 7:0 ] rise_count_0 0 xf r/w 0 x 122 txen_sm_ 3 [ 7:0 ] rise_count_1 0 x 0 r/w 0 x 123 txen_sm_ 4 [ 7:0 ] fall_count_0 0 xff r/w 0 x 124 txen_sm_ 5 [ 7:0 ] fall_count_1 0 xff r/w 0 x 12d d evice_ config_reg0 [ 7:0 ] d evice_ config_0 must be set to 0x8b for proper digital datapath configuration. 0 x 46 r/w 0 x 12f die_temp_ ctrl 0 [ 7 :1] reserved reserved . 0x 1 0 r/w 0 auxadc_ enable 1 = enable auxadc block . 0 x 0 r/w 0x 132 die_temp 0 [ 7:0 ] die_temp_lsb auxadc readback value bits [7:0] , lsb . 0 x 0 r 0 x 133 die_temp 1 [ 7:0 ] die_temp_msb auxadc readback value bits [15:8] , msb . 0 x 0 r 0 x 134 die_temp_ update [ 7:1 ] reserved reserved. 0 x 0 r 0 die_temp_ update d ie tempera ture update. w hen update d , new temperature code is received . 0 x 0 r/w 0 x 135 dc_offset_ ctrl [7: 1 ] reserved reserved. 0 x 0 r 0 dc_offset_on 1 = enable dc offset module . 0 x 0 r/w 0 x 136 ipath_dc_off - set_ 1 part 0 [ 7:0 ] ipath_dc_ offset_ 1 part 0 lsb of fi rst part of dc offset value for i path . 0 x 0 r/w 0 x 137 ipath_dc_off - set_1part1 [ 7:0 ] ipath_dc_ offset_ 1 part 1 msb of first part of dc offset value for i path . 0 x 0 r/w 0 x 138 qpath_dc_ offset_ 1 par t 0 [ 7:0 ] qpath_dc_ offset_ 1 part 0 lsb of first part of dc offset value for q path . 0 x 0 r/w 0 x 139 qpath_dc_ offset_ 1 part 1 [ 7:0 ] qpath_dc_ offset_ 1 part 1 msb of first part of dc offset value for q path . 0 x 0 r/w 0 x 13a ipath_dc_ offset_ 2 par t [ 7:5 ] reserved reserved. 0 x 0 r [ 4:0 ] ipath_dc_ offset_ 2 part sec ond part of dc offset value for i path . 0 x 0 r/w
data sheet AD9154 rev. b | page 103 of 124 addr. name bits bit name settings description reset access 0 x 13b qpath_dc_ offset_ 2 par t [ 7:5 ] reserved reserved. 0 x 0 r [ 4:0 ] qpath_dc_ offset_ 2 part second part of dc offset value for q path . 0 x 0 r/w 0 x 13c idac_dig_ gain 0 [ 7:0 ] idac_dig_ gain 0 lsb of i da c digital gain . 0 x 0 r/w 0 x 13d idac_dig_ gain 1 [ 7:4 ] reserved reserved. 0 x 0 r [ 3:0 ] idac_dig_ gain 1 msb of i dac digital gain . 0 x 8 r/w 0 x 13e qdac_dig_ gain 0 [ 7:0 ] qdac_dig_ gain 0 lsb of q dac digital gain . 0 x 0 r/w 0 x 13f qdac_dig_ gain 1 [ 7:4 ] r eserved reserved. 0 x 0 r [ 3:0 ] qdac_dig_ gain 1 msb of q dac digital gain . 0 x 8 r/w 0 x 140 gain_ramp_ up_step 0 [ 7:0 ] gain_ramp_ up_step 0 lsb of digital gain rises . 0 x 4 r/w 0 x 141 gain_ramp_u p_step 1 [ 7:4 ] reserved reserved. 0 x 0 r [ 3:0 ] gain_r amp_ up_step 1 msb of digital gain rises . 0 x 0 r/w 0 x 142 gain_ramp_d own_step 0 [ 7:0 ] gain_ramp_ down_step 0 lsb of digital gain drops . 0 x 9 r/w 0 x 143 gain_ramp_d own_step 1 [7: 4 ] reserved reserved. 0 x 0 r [ 3:0 ] gain_ramp_ down_step 1 msb of digital g ain drops . 0 x 0 r/w 0 x 146 device_confi g_reg1 [ 7:0 ] device_ config_ 1 must be set to 0x01 during start up . 0 x 0 r/w 0 x 147 blsm_ stat [ 7 :6] be_rotate_req be_rotate_req forced val ue . 0 x 0 r/w [5: 0 ] reserved reserved . 0 x 0 r/w 0 x 14b prbs 7 prbs_good _q good data indicator imaginary channel . 0 x 0 r 0 incorrect sequence detected . 1 correct prbs sequence detected . 6 prbs_good_i good data indicator real channel . 0 x 0 r 0 incorrect sequence detected . 1 c orrect prbs sequence detected . 5 reserved reserved. 0 x 0 r [ 4 :3] reserved reserved . 0 x 1 r/w 2 prbs_mode polynomial select . 0 x 0 r/w 0 7 - bit: x 7 + x 6 + 1 1 15 - bit: x 15 + x 14 + 1 1 prbs_reset reset error counters . 0 x 0 r/w 0 normal operation . 1 reset counters . 0 prbs_en enable prbs checker . 0 x 0 r/w 0 disable . 1 enable . 0 x 14 c prbs_error_i [ 7:0 ] prbs_count_i error count value real channel . 0 x 0 r 0x1 4 d prbs_error_q [ 7:0 ] prbs_count_q error count value imagin ary channel . 0 x 0 r
AD9154 data sheet rev. b | page 104 of 124 addr. name bits bit name settings description reset access 0 x 1 b 0 dac p llt0 7 vco_pd_in vco pd . 0 x 1 r/w 0 if power machine disabled this powers up the vco . 1 if power machine disabled this powers down the vco . 6 vco_pd_ptat pd ptat current gen vco . 0 x 1 r/w 1 if power machine disabled this powers down the vco ptat gen . 0 if power machine disabled this powers up the vco ptat gen . 5 vco_pd_alc pd alc circuit in vco . 0 x 1 r/w 1 if power machine disabled this powers down the vco alc . 0 if power machine disabled this powers up the vco alc . 4 synth_pd pd total synth esizer /reset machine . 0 x 1 r/w 0 if power machine disabled this powers up the synthesizer . 1 if power machine disabled this powers down the synthesizer . 3 ldo_pd pd ldo . 0 x 1 r/w 0 if power machine disabled this powers up the ldo . 1 if power machine disabled this powers down the ldo . 2 reserved reserved. 0 x 0 r 1 logen_pd pd lo generator . 0 x 1 r/w 0 if power machine disabled this powers up the prescaler/dac clock gen . 1 if power machine disabled this powers down the prescaler/dac clock gen . 0 res erved reserved. 0 x 0 r 0 x 1 b 1 dac p llt1 [7:4] reserved reserved. 0 x 0 r [3:2] pfd_delay pfd delay . 0 x 1 r/w 0 shortest delay . 1 longer delay . 2 longer delay still . 3 longest delay . 1 pfd_edge p fd clock edge . 0 x 0 r/w 0 reference rising edge . 1 reference falling edge . 0 reserved reserved. 0 x 0 r 0 x 1 b 2 dac p llt2 7 ext_alc_word_ en force alc word externally . 0 x 0 r/w 0 norm operation auto alc . 1 ma nually set alc . [6:0] ext_alc_word external alc word . 0 x 0 w 0 x 1 b 3 dac p llt3 [7:0] ext_band1 bottom bit of vco tuning band to be forced . 0 x 0 w 0 x 1 b 4 dac p llt4 7 byp_load_delay bypass load delay . 0 x 0 r/w [6:3] vco_cal_offset starting of fset for vco calibration . 0 xf r/w 2 reserved reserved. 0 x 0 r 1 ext_band_en force vco tuning band externally . 0 x 0 r/w 0 normal autocal mode . 1 manual for vco band . 0 ext_band2 external band msb . 0 x 0 w 0 x 1 b 5 dac p llt5 [7:4] init_alc_value initial alc sweep value . 0 x 8 r/w [3:0] vco_var varactor kvo setting . 0 x 3 r/w
data sheet AD9154 rev. b | page 105 of 124 addr. name bits bit name settings description reset access 0 x 1 b 6 dac p llt6 7 reserved reserved. 0 x 0 r 6 poresetb_vco reset for vco logic . 0 x 1 r/w [5:4] ext_vco_bitsel external vco bitsel . 0 x 0 r/w [3:0] vco_lvl_out vco amplitude control . 0 xa r/w 0 x 1 b 7 dac p llt7 7 ld_synth manual recal ibration of synthesizer . 0 x 0 r/w 1 enable circuitry to reduce the voltage of the cal offset target point . 0 disable circuitry to reduce the voltage of the cal offset target point . 6 reserved reserved. 0 x 0 r [5:0] cp_ibleed charge pump offset . 0 x 0 r/w 0 x 1 b 8 dac p llt8 7 reserved reserved. 0 x 0 r 6 comp_out cp calibration comparator output . 0 x 0 r 5 cp_ca l_done cp calibration has completed . 0 x 0 r 4 vco_cal_in_ prog vco calibration occurring. 0 x 0 r [3:0] cp_calbits calibrated cp outcome . 0 x 0 r 0 x 1 b 9 dac p llt9 7 half_vco_cal_ clk slow down vco calibration clock . 0 x 0 r/w 6 dither_mode dither mode not used . 0 x 0 r/w 5 machine_ enable pll power mode machine enable . 0 x 1 r/w 4 cp_offset_off turn off cp offset . 0 x 1 r/w 3 force_cp_ calbits force exter nal cp cal code . 0 x 0 r/w 0 cp calibration auto if device off . 1 cp calibration manual i f device off . 2 cap_cal_en enable cp calibration . 0 x 1 r/w 0 disable charge pump calibration . 1 enable charge pump calibration . [1:0] cp_test cp test mode s . 0 x 0 r/w 0 x 1 ba dac p llt a [7:4] machine_state power - up machine state . 0 x 0 r [3:0] fcp_calbits external cp calibration bits to drive . these are the externally forced calibration bits for the charge pump in the pll when the power - up machine is not in use. the power - up mach ine automatically calibrate s the charge pump and store s the value in the device. 0 x 0 r/w 0 x 1 bb dac p lltb [7:5] reserved reserved. 0 x 0 r [4:3] vco_bias_tcf temp erature co efficient for vco bias . 0 x 1 r/w [2:0] vco_bias_ref vco bias control . 0x 4 r/w 0x1bc dac p lltc 7 vco_byp_biasr bypass vco bias resistor . 0x0 r/w [6:5] reserved reserved . 0x0 r/w 4 vco_comp_byp_ biasr bypass resistor in vco comparator . 0x0 r/w 3 prsc_highr prsc configuration . 0x0 r/w 2 last_alc_en enable last alc . 0x0 r/w [1:0] prsc_bias_ctrl prsc bias control . 0x0 r/w 0 x 1 bd dac p lltd [7:4] reserved reserved. 0 x 0 r 3 vco_cal_ref_ mon sent control voltage to outside world . 0 x 0 r/w [2:0] vco_cal_ref_ tcf temp erature co efficient for calibration re f erence . 0 x 0 r/w
AD9154 data sheet rev. b | page 106 of 124 addr. name bits bit name settings description reset access 0 x 1 be dac p llte [7:4] reserved reserved. 0 x 0 r 3 vco_pdo_vr varactor reference power - down override . 0 x 0 r/w 2 vco_pdo_vrtcf varactor temp erature co efficient power - down 0 x 0 r/w 1 vco_pdo_ caltcf calibration temp eratur e co efficient power - down. 0 x 0 r/w 0 vco_pdo_ vcobuf vco buffer pd override . 0 x 0 r/w 0 x 1 bf dac p lltf 7 i_cal_en vco band calibration enable . 0 x 1 r/w [6:4] i_alc_wait_d vco calibration wait for alc cal from band change . 0 x 0 r/w [3:2] i_c al_count calibration count length . 0 x 3 r/w [1:0] fdbck_delay feedback clock advance . 0 x 1 r/w 0 x 1 c 0 dacpllt10 [7:6] reserved reserved. 0 x 0 r 5 use_new_cal use new calibrator . 0 x 1 r/w 0 use old cal ibrator . 1 use new ca l ibrator . 4 double_f 0 _cal_ cnt increase calibrator count by 2 old cal ibrator machine . 0 x 0 r/w [3:2] lockdetect_co unt counter length for lock det ector . 0 x 3 r/w [1:0] lock_mode lock detector mode . 0 x 2 r/w 0 x 1 c 1 dacpllt11 7 reserved reserved. 0 x 0 r 6 cp_lvl_det_pd level detector power - down . 0 x 0 r/w [5:3] cp_vl_low low level detect voltage . 0 x 2 r/w [2:0] cp_vl_high high level detection point . 0 x 5 r/w 0 x 1 c 2 dacpllt15 7 sdm_bp bypass sigma delta . 0 x 1 r/w 6 sdm_pd power -do wn sdm . 0 x 0 r/w [5:4] reserved reserved. 0 x 0 r [3:0] sdm_prog program sdm . 0 x 0 r/w 0 x 1 c 3 dacpllt16 7 reserved reserved. 0 x 0 r 6 sdm_prog3 sif clock . 0 x 0 r/w 5 sdm_prog2 sif preset b ar . 0 x 0 r/w [4:0] sdm _prog1 sif address . 0 x 0 r/w 0 x 1 c 4 dacpllt17 7 reserved reserved. 0 x 0 r [6:4] vco_var_ref_ tcf varactor reference temp erature co efficient . 0 x 3 r/w [3:0] vco_var_off varactor offset . 0 x 3 r/w 0 x 1 c 5 dacpllt18 [7:4] reserved reserved. 0 x 0 r [3:0] vco_var_ref vco vara c tor reference . 0 x 8 r/w 0 x 200 master_pd [7:1] reserved reserved. 0 x 0 r 0 spi_pd_master power down the entire jesd 204b rx analog (all eight channels + bias). 0 x 1 r/w 0 x 201 phy_pd [7:0] unusedlanes spi override to p ower down the individual phys. 0 x 0 r/w set bit x to power down the corresponding serdinx phy . 0 x 203 generic_pd [7: 2 ] reserved reserved. 0 x 0 r 1 spi_sync1_pd power down lvds buffer for syncout0 . 0 x 0 r/w 0 spi _sync2_pd power down lvds buffer for syncout1 . 0 x 0 r/w 0 x 206 cdr_reset [7:1] reserved reserved. 0 x 0 r 0 spi_cdr_resetn resets the digital control logic for all phys. 0 x 1 r/w 0 cdr logic is reset . 1 cdr lo gic is operational .
data sheet AD9154 rev. b | page 107 of 124 addr. name bits bit name settings description reset access 0x230 cdr_ operating_ mode_reg_0 [7:6] reserved reserved . 0x0 r/w 5 halfrate enables half rate cdr operation . 0x1 r/w 0 disables cdr half rate operation, data rate 6 gbps . 1 enables cdr half rate operation , data rate > 6 gbps . [4:2] reserved reserved . 0x0 r/w 1 cdr_oversamp enables oversampling of the input data. set to 1 when 1.44 gbps lane rate 2.88 gbps . 0x0 r/w 0 reserved reserved . 0x0 r/w 0 x 268 eq_bias_reg [ 7:6 ] eq_power_ mode used t o control the equalizer power/ insertion loss capability . 0 x 1 r/w 0 normal mode . 1 low power . [5: 0 ] reserved reserved . 0x 32 r/w 0x2 80 synth_ enable_ cntrl [7:3] reserved reserved . 0 x 0 r 2 spi_recal_ synth set this bit h igh to re - run all of the serdes pll calibration routines. 0 x 0 r/w set this bit low again to allow for additional re - calibrations. rising edge causes the cali bration. 1 reserved reserved . 0 x 0 r/w 0 spi_enable_ synth enable the serdes pll. 0 x 0 r/w setting this bit turns on all currents and proceeds to calibrate the pll. make sure reference clock and division ratios are correct before enab ling this bit. 0 x 281 pll_status [7:6] reserved reserved . 0 x 0 r 5 spi_cp_over_ range_high_rb applies if spi_vco_output_level = 0. if set, the cp output is above cp level threshold high . 0 x 0 r 0 charge pump output is below cp_level_thres hold_high. 1 charge pump output is above cp_level_threshold_high. 4 spi_cp_over_ range_low_rb applies if spi_vco_output_level = 0. if set, the cp output i s below cp level threshold low . 0 x 0 r 0 charge pump output is above cp _level_threshold_low. 1 charge pump output is below cp_level_threshold_low. 3 spi_cp_cal_ valid_rb this bit tells the user if the charge pump cal has completed. 0 x 0 r 0 charge pump calibration is not valid. 1 cha rge pump calibration is valid. 2 spi_vco_cal_in _progress_rb this bit set indicates that a vco calibration is running . 0 x 0 r 0 vco calibration is not running. 1 vco calibration is running. 1 spi_currents_ ready_rb 0 x 0 r 0 pll bias currents are not ready. 1 pll bias currents are ready. 0 spi_pll_lock_ rb if set, the synth locked in the number of clock cycles set by lock detect count . 0 x 0 r 0 pll is not locked. 1 pll is locked.
AD9154 data sheet rev. b | page 108 of 124 addr. name bits bit name settings description reset access 0 x 284 loop_ filter_ 1 [ 7:4 ] loop_filter_ 1 loop filter configuration setting . 0 x 7 r/w [ 3:0 ] 0 x 7 r/w 0 x 285 loop_ filter_ 2 [ 7:4 ] loop_filter_ 2 loop filter configuration setting . 0 x 8 r/w [ 3:0 ] 0 x 7 r/w 0 x 286 loop_ filter_ 3 [7: 4 ] loop_filter_ 3 loop filter configuration setting . 0 x 0 r/w [ 3:0 ] 0 x 8 r/w 0 x 287 cp_current 7 reserved reserved . 0 x 0 r 6 spi_serdes_ logen_power_ mode 0 x 0 r/w 0 power mode 0 . 1 power mode 1 . [5:0] spi_cp_current cp current se tting. 0x3f r/w 0 x 289 ref_clk_ divider_ldo [7:4] reserved reserved. 0 x 0 r 3 spi_ldo_ref_ sel selects ldo reference to be from the band gap or a voltage divider (vdd/ 2 ). 0 x 0 r/w 0 select band gap for reference. 1 select voltag e divider (vdd/ 2 ) for reference. 2 spi_ldo_ bypass_filt bypasses filter on ldo reference input. 0 x 1 r/w 0 filter enabled. 1 filter bypassed. [1:0] spi_cdr_ oversamp enable oversampling of input data . 0 x 0 r/w the valid options are: 1 , 2, and 4 . 1 works for half rate 6.25 gbps to 12.5 gbps . 1 works for full rate 3.125 gbps to 6.25 gbps . 2 works for full rate 1.625 gbps to 3.125 gbps (2 oversampling) . 4 works for f ull rate 812.5 mbps to 1.625 gbps (4 oversampling) . oversampling set in register 0x230 . 0 no oversampling. data rate > 6 gbps. 1 oversample by 2 . 3 gbps < data rate 6 gbps. 2 oversample by 4. 1.5 gbps < data rate 3 gbps. 0 x 28a vco_ldo [7:0] spi_serdes_ldo _config vco ldo setting . 0 x 2 b r/w 0 x 28b pll_pd_reg 7 reserved reserved . 0 x 0 r/w 6 spi_vco_pd vco enable . 0 x 1 r/w 0 vco enabled . 1 vco disabled . 5 spi_vco_pd_ ptat 0 x 1 r/w 4 spi_vco_pd_alc 0 x 1 r/w 3 spi_syn_pd 0 x 1 r/w 2 spi_serdes_ ldo_pd pd ldo . 0 x 1 r/w 0 ldo enabled . 1 ldo disabled . 1 spi_serdes_ logen_pd_ outbuf pd divider buff er . 0 x 1 r/w 0 buffer enabled . 1 buffer disabled .
data sheet AD9154 rev. b | page 109 of 124 addr. name bits bit name settings description reset access 0 spi_serdes_ logen_pd_core pd log en dividers . 0 x 1 r/w 0 dividers enabled . 1 dividers disabled . 0 x 290 alc_ varactor [7:4] spi_init_alc_ value alc value setting . 0 x 8 r/w [3:0] spi_vco_ varactor vco kv setting . 0 x 3 r/w 0 x 291 vco_output [7:4] reserved reserved . 0 x 4 r/w [3:0] spi_vco_ output_level vco output level setting . 0 x 9 r/w 0 x 294 cp_config 7 spi_half_vco_ cal_clk 0 x 1 r/w 6 spi_dither_ mode 0 x 0 r/w 5 spi_enable_ machine 0 x 1 r/w 4 spi_cp_offset_ off 0 x 1 r/w 3 spi_cp_force_ calbits 0 x 0 r/w 2 spi_cp_cal_en 0 x 0 r/w [1:0] spi_cp_test 0 x 0 r/w 0 x 296 vco_bias_1 [7:5] reserved reserved . 0 x 0 r/w [4:3] spi_vco_bias_ tcf 0 x 1 r/w [2:0] spi_vco_bias_ ref cp calibration control . 0 x 4 r/w 0 x 297 vco_bias_2 [7:6] reserved reserved . 0 x 0 r 5 spi_vco_bypass _bias_dac_r 0 x 0 r/w 4 spi_vco_comp_ bypass_biasr 0 x 0 r/w 3 spi_prescale_ bypass_r 0 x 0 r/w 2 spi_last_alc_ en 0 x 0 r/w [1:0] spi_prescale_ bias 0 x 0 r/w 0 x 299 vco_pd_ overrides [7:4] reserved 0 x 0 r/w 3 spi_vco_pd_ overr ide_var_ ref 0 x 0 r/w 2 spi_vco_pd_ override_var_ ref_tcf 0 x 0 r/w 1 spi_vco_pd_ override_cal_ tcf 0 x 0 r/w 0 spi_vco_pd_ override _ vcobuf 0 x 0 r/w
AD9154 data sheet rev. b | page 110 of 124 addr. name bits bit name settings description reset access 0 x 29a vco_cal 7 spi_vco_cal_en 0 x 1 r/w [6:4] spi_vco_cal_ alc_wait 0 x 7 r/w [3:2] spi_vco_cal_ count 0 x 3 r/w [1:0] spi_fb_clock_ adv 0 x 2 r/w 0 x 29c cp_level_ detect 7 reserved reserved . 0 x 0 r 6 spi_cp_level_ det_pd 0 x 0 r/w [5:3] spi_cp_level_ threshold_low 0 x 2 r/w [2:0] spi_cp_level_ threshold_ high 0 x 7 r/w 0 x 29f vco_ varactor_ control_0 7 reserved 0 x 0 r [6:4] spi_vco_varac - tor_ref_tcf 0 x 3 r/w [3:0] spi_vco_varac - tor_offset 0 x 3 r/w 0 x 2 a 0 vco_ varactor_ control_1 [7:4] reserved 0 x 0 r [3:0] spi_vco_ varactor_ref 0 x 8 r/w 0 x 2 a 7 term_blk1_ ctrlreg0 [7:1] reserved reserved. 0 x 0 r 0 spi_i_tune_r_ cal_termblk1 rising edge of this bit starts a termination calibration routine. 0 x 0 r/w 0 x 2 ae term_blk2_ ctrlreg0 [7:1] reserved reserved. 0 x 0 r 0 spi_i_tune_r_ cal_termblk2 rising edge of this bit starts a termination calibration routine. 0 x 0 r/w 0 x 300 general_ jrx_ctrl_0 7 reserved reserved. 0 x 0 r 6 checksummode jesd 204b link parameter checksum calculation method. 0 x 0 r/w 0 checksum is the sum of fields . 1 checksum is the sum of octets . [ 5 :4] reserved reserved 0 x 0 r/w 3 duallink this register selects either single link or dual link mo de . 0 x 0 r/w 0 single link mode . 1 dual link mode . 2 currentlink to select which qbd register map to work with . 0 x 0 r/w 0 user access to qbd_0 registers . 1 user access to qbd_1 registers . [1:0] e nlinks u sed to bring up jesd 204b rx digital when all link parameters are programmed and all clocks are ready 0 x 0 r/w bit 0 applies to link 0 while bit 1 applies to link 1 . link 1 is only available in dual link mode. both links may be brough t up separately or together. 0 x 301 general_ jrx_ctrl_1 [7:3] reserved reserved. 0 x 0 r [2:0] subclassv_ local jesd 204b subclass 0 x 1 r/w 0 s ubclass 0 1 s ubclass 1
data sheet AD9154 rev. b | page 111 of 124 addr. name bits bit name settings description reset access 0 x 302 dyn_link_ latency_0 [7:5] reserved reserved. 0 x 0 r [4:0] dyn_link_ latency_0 link 0 dynamic link latency . 0 x 0 r latency between current deframer lmfc and the global lmfc . 0 x 303 dyn_link_ latency_1 [7:5] reserved reserved. 0 x 0 r [4:0] dyn_link_ latency_1 link 1 dynamic link laten cy . 0 x 0 r latency between current deframer lmfc and the global lmfc . 0 x 304 lmfc_ delay_0 [7:5] reserved reserved. 0 x 0 r [4:0] lmfcdel 0 delay in frame clock cycles for global lmfc for link 0 . 0 x 0 r/w 0 x 305 lmfc_ delay_1 [7:5] reserved reserved. 0 x 0 r [4:0] lmfcdel 1 delay in frame clock cycles for global lmfc for link 1 . 0 x 0 r/w 0 x 306 lmfcvar 0 [7:5] reserved reserved. 0 x 0 r [4:0] lmfcvar 0 location in rx lmfc where jesd 204b words are read out from buffer . 0 x 6 r/w thi s setting should not be more than 10 . 0 x 307 lmfcvar 1 [7:5] reserved reserved. 0 x 0 r [4:0] lmfcvar 1 location in rx lmfc where jesd 204b words are read out from buffer . 0 x 6 r/w this setting should not be more than 10 . 0 x 308 xbar_ln_0_1 [7 :6] reserved reserved. 0 x 0 r [5:3] xbarval 1 logic lane 1 source. selects a physical lane to be mapped onto logical lane 1 . 0 x 1 r/w data is from serdin x . [2:0] xbarval 0 logic lane 0 source. selects a physical lane to be mapped onto logical lane 0 . 0 x 0 r/w data is from serdin x . 0 x 309 xbar_ln_2_3 [7:6] reserved reserved. 0 x 0 r [5:3] xbarval 3 logic lane 3 source. selects a physical lane to be mapped onto logical lane 3 . 0 x 3 r/w data is from serdin x . [2:0] xbarval 2 logic lane 2 source. selects a physical lane to be mapped onto logical lane 2 . 0 x 2 r/w data is from serdin x . 0 x 30a xbar_ln_4_5 [7:6] reserved reserved. 0 x 0 r [5:3] xbarval 5 logic lane 5 source. selects a physical lane to be mapped onto logical lane 5 . 0 x 5 r/w data is from serdin x . [2:0] xbarval 4 logic lane 4 source. selects a physical lane to be mapped onto logical lane 4 . 0 x 4 r/w data is from serdin x . 0 x 30b xbar_ln_6_7 [7:6] reserved reserved. 0 x 0 r [5:3] xbarval 7 logic lane 7 source. selects a physical lane to be mapped onto logical lane 7 . 0 x 7 r/w data is from serdinx . [2:0] xbarval 6 logic lane 6 source. selects a physical lane to be mappe d onto logical lane 6 . 0 x 6 r/w data is from serdinx . 0 x 30c fifo_ status_ reg_0 [7:0] lane_fifo_full fifo full flags for each logical lane. a full fifo indicates an error in the jesd204b configuration or with a system clock. if the fifo fo r lane x is full, bit x in this register will be high . 0 x 0 r
AD9154 data sheet rev. b | page 112 of 124 addr. name bits bit name settings description reset access 0 x 30d fifo_status_ reg_1 [7:0] lane_fifo_ empty fifo empty flags for each logical lane. an empty fifo indicates an error in the jesd204b configuration or with a system clock. if the fifo for la ne x is empty, bit x in this register will be high . 0 x 0 r 0 x 312 syncb_ gen_1 [7: 6 ] reserved reserved . 0 x 0 r/w [5:4] syncb_err_dur duration of syncoutx low for error. the duration applies to both syncout0 and syncout1 . a sync error is asserted at the end of a multiframe whenever one or more disparity, not in table or unexpected control character errors are encountered. 0x0 r/w 0 ? pclk cycle . 1 1 pclk cycle . 2 2 pclk cycles . [3:0] reserved reserved . 0 x 0 r/w 0 x 314 spi_sync_ ctrl [7: 1 ] reserved reserved . 0 x 0 r 0 spi_sync_clk_ sel serdes spi configuration . 0 x 0 r/w 0 1 setting in phy layer setup . 0 x 315 phy_prbs_ test_en [7:0] phy_test_en set bit x to enable the phy test for lane x . 0 x 0 r/w 0 x 316 phy_prbs_ test_ctrl 7 reserved reserved. 0 x 0 r [6:4] phy_src_err_ cnt report lane error count . 0 x 0 r/w [3:2] phy_prbs_ pat_sel to select prbs pattern for phy ber test . 0 x 0 r/w 0 prbs7 . 1 prbs15 . 2 prbs31 . 3 not used . 1 phy_test_start to start and stop the phy prbs test . 0 x 0 r/w 0 test not started . 1 test started . 0 phy_test_reset reset phy prbs test state machine, and error counters . 0 x 0 r/w 0 not reset . 1 reset . 0 x 317 phy_prbs_ test_thres - hold_lobits [7:0] phy_prbs_ threshold_ lobits bits [7:0] of the 24 - bit threshold value to set the error flag for phy prbs test . 0x0 r/w 0 x 318 phy_prbs_ test_thresh old_midbits [7:0] phy_prbs_ threshold_ midbits bits [15:8] of the 24 - bit threshold value to set the error flag for phy prbs test . 0 x 0 r/w 0 x 319 phy_prbs_ test_thres - hold_hibits [7:0] phy_prbs_ threshold_ hibits bits [23: 16] of the 24 - bit threshold value to set the error flag for phy prbs test . 0 x 0 r/w 0 x 31a phy_prbs_ test_errcnt_ lobits [7:0] phy_prbs_err_ cnt_lobits bits [7:0] of the 24 - bit reported phy bert error count from selected lane . 0 x 0 r 0 x 31b phy_prbs_ test_er rcnt_ midbits [7:0] phy_prbs_err_ cnt_midbits bits [15:8] of the 24 - bit reported phy bert error count from selected lane . 0 x 0 r
data sheet AD9154 rev. b | page 113 of 124 addr. name bits bit name settings description reset access 0 x 31c phy_prbs_ test_errcnt_ hibits [7:0] phy_prbs_err_ cnt_hibits bits [23:16] of the 24 - bit reported phy bert error count fro m selected lane . 0 x 0 r 0 x 31d phy_prbs_ test_status [7:0] phy_prbs_pass each bit is for the corresponding lane. 0 xff r report phy bert pass/fail for each lane . 0 x 32c short_tpl_ test_0 [7:6] reserved reserved. 0 x 0 r [5:4] short_tpl_sp_ sel sho rt transport layer sample select. select which sample to check from a specific dac . 0 x 0 r/w 0 sample 0 . 1 sample 1 . 2 sample 2 . 3 sample 3 . [3:2] short_tpl_m_ sel short transport layer tes t dac select . select which dac to check . 0 x 0 r/w 0 dac 0 . 1 dac 1 . 2 dac 2 . 3 dac 3 . 1 short_tpl_test _reset sho rt transport layer test rese t. resets the result of short transport layer test at short_tpl_dif f. 0 x 0 r/w 0 not reset . 1 reset . 0 short_tpl_ test_en sho rt transport layer test enable . enable short transport layer test. 0 x 0 r/w 0 disable . 1 enable . 0 x 32d short_tpl_ test_1 [7:0] short_tpl_ref_ sp_lsb short transpo rt layer reference sample lsb. this is the lower 8 bits of expected dac sample. it is used to compare with the received dac sample at the output of jesd 204b rx . 0 x 0 r/w 0 x 32e short_tpl_ test_2 [7:0] short_tpl_ref_ sp_msb short tran sport layer test reference sample msb. this is the upper 8 bits of expected dac sample. it is used to compare wit h the received sample at jesd rx output. 0 x 0 r/w 0 x 32f short_tpl_ test_3 [7:1] reserved reserved. 0 x 0 r 0 short_tpl_fail short transport layer t est fail. this bit show s if the selected dac sample matches the reference sample. if they match test pass; otherwise test fail. 0 x 0 r 0 test pass . 1 test fail . 0 x 333 device_co n - fig_reg2 [7: 0 ] reserved must be set to 0x1 for correct jesd204b receiver operation . 0 x 0 r/w 0 x 334 jesd_bit_ inverse_ctrl [7:0] invlanes logic lane invert. set bit x high to invert the jesd 204b deserialized data on logical lane x . 0 x 0 r/w 0 x 400 did_reg [7:0] did_rd did is the de vice id no . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 x 401 bid_reg [7:4] adjcnt_rd adjcnt is the adjustment resolution to dac lmfc . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. [3:0] bid_rd bi d is the bank id extension to did. 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b.
AD9154 data sheet rev. b | page 114 of 124 addr. name bits bit name settings description reset access 0 x 402 lid0_reg 7 reserved reserved. 0 x 0 r 6 adjdir_rd adjdir is the direction to adjust dac lmfc . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 5 phadj_rd phadj is the phase adjustment request to dac . 0 x 0 r link information received on lane 0 as specified in section 8.3 of je sd 204b. [4:0] lid0_rd lid0 is the lane identification for lane 0 . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 x 403 scr_l_reg 7 scr_rd scr is the tx scrambling status . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 scrambling is disabled . 1 scrambling is enabled . [6:5] reserved reserved. 0 x 0 r [4:0] l_rd l is the number of lanes per converter device . 0 x 0 r lin k information received on lane 0 as specified in section 8.3 of jesd 204b. 0 1 lane per converter device . 1 2 lanes per converter device . 3 4 lanes per converter device . 0 x 404 f_reg [7:0] f_rd f is the number of oct ets per frame . 0 x 0 r settings of 1, 2, and 4 are valid . link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 1 octet per frame . 1 2 octets per frame . 3 4 octets per frame . 0x40 5 k_reg [7:5] reserved reserved. 0 x 0 r [4:0] k_rd k is the number of frames per multiframe . 0 x 0 r settings of 16 or 32 are valid. link information received on lane 0 as specified in section 8.3 of jesd 204b. 01111 = 16 . 11111 = 32 . 0 x 406 m_reg [7:0] m_rd m is the number of converters / device . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. must be 1,2, or 4 to be compatible with AD9154 0 1 converter per device . 1 2 converters per device . 3 4 converters per device . 0 x 407 cs_n_reg [7:6] cs_rd cs is the number of control bits/sample . 0 x 0 r link information received o n lane 0 as specified in section 8.3 of jesd 204b. must be 0 to be compatible with AD9154 . 5 reserved reserved. 0 x 0 r [4:0] n_rd n = converter resolution . 0 x 0 r 0 x 408 np_re g [7:5] subclassv_rd subclassv is the device subclass version . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b.
data sheet AD9154 rev. b | page 115 of 124 addr. name bits bit name settings description reset access [4:0] np_rd np is the total number of bits/sample . 0 x 0 r link information received on l ane 0 as specified in section 8.3 of jesd 204b. = 16 bits per sample . 0 x 409 s_reg [7:5] jesdv_rd jesdv is the jesd204 version . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 jesd204a . 1 jesd204b . [4:0] s_rd s is the number of samples/converte r per frame cycle . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 one sample per converter per frame . 1 two sampl es per converter per frame . 0 x 40a hd_cf_reg 7 hd_rd hd is the high density format . 0 x 0 r refer to section 5.1.3 of jesd204b standard . link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 low density mode . 1 high density mode . [6:5] reserved reserved. 0 x 0 r [4:0] cf_rd cf is the number of control word s per frame clock period per link . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd204b. must be 0 to be compatible to the AD9154 . 0 x 40b res1_reg [7:0] res1_rd reserved field 1 . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 x 40c res2_reg [7:0] res2_rd reserved field 2 . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 x 40d checksum_ reg [7:0] lane0checksu m _rd checksum for lane 0 . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 x 40e compsum0_ reg [7:0] fcmp0_rd computed checksum for lane 0 . 0 x 0 r the jesd204b rx computes the checksum of the link information received on lane 0 as specified in section 8.3 of jesd204b. the computati on method is set by the checksummode bit ( register 0x300[6]) and should match the likewise calculated checksum in register 0x40d . 0 x 412 lid1_reg [7:5] reserved reserved. 0 x 0 r [4:0] lid1_rd lane identification for lane 1 . 0 x 0 r link infor mation received on lane 0 as specified in section 8.3 of jesd 204b. 0 x 415 checksum1_ reg [7:0] fchk1_rd checksum for lane 1 . 0 x 0 r link information received on lane 0 as specified in section 8.3 of jesd 204b. 0 x 416 compsum1_ reg [7:0] fcmp1_rd computed checksum for lane 1. s ee description for register 0x40e. 0 x 0 r 0 x 41 a lid2_reg [7:5] reserved reserved. 0 x 0 r [4:0] lid2_rd lane identification for lane 2 . 0 x 0 r
AD9154 data sheet rev. b | page 116 of 124 addr. name bits bit name settings description reset access 0 x 41d checksum2_ reg [7:0] fchk2_rd checksum for lane 2 . 0 x 0 r 0 x 41e c ompsum2_ reg [7:0] fcmp2_rd computed checksum for lane 2. s ee description for register 0x40e. 0 x 0 r 0 x 422 lid3_reg [7:5] reserved reserved. 0 x 0 r [4:0] lid3_rd lane identification for lane 3 . 0 x 0 r 0 x 425 checksum3_ reg [7:0] fchk3_rd checksu m for lane 3 . 0 x 0 r 0 x 426 compsum3_ reg [7:0] fcmp3_rd computed checksum for lane 3 (see description for register 0x40e) . 0 x 0 r 0 x 42 a lid4_reg [7:5] reserved reserved. 0 x 0 r [4:0] lid4_rd lane identification for lane 4 . 0 x 0 r 0 x 42d checksum4_ reg [7:0] fchk4_rd checksum for lane 4 0 x 0 r 0 x 42e compsum4_ reg [7:0] fcmp4_rd computed checksum for lane 4 (see description for register 0x40e) . 0 x 0 r 0 x 432 lid5_reg [7:5] reserved reserved. 0 x 0 r [4:0] lid5_rd lane identification for lan e 5 . 0 x 0 r 0 x 435 checksum5_ reg [7:0] fchk5_rd checksum for lane 5 . 0 x 0 r 0 x 436 compsum5_ reg [7:0] fcmp5_rd computed checksum for lane 5 (see description for register 0x40e) . 0 x 0 r 0 x 43a lid6_reg [7:5] reserved reserved. 0 x 0 r [4:0] lid6_rd lane identification for lane 6 . 0 x 0 r 0 x 43d checksum6_ reg [7:0] fchk6_rd checksum for lane 6 . 0 x 0 r 0 x 43e compsum6_ reg [7:0] fcmp6_rd computed checksum for lane 6 (see description for register 0x40e) . 0 x 0 r 0 x 442 lid7_reg [7:5] reserved reserv ed. 0 x 0 r [4:0] lid7_rd lane identification for lane 7 . 0 x 0 r 0 x 445 checksum7_ reg [7:0] fchk7_rd checksum for lane 7 . 0 x 0 r 0 x 446 compsum7_ reg [7:0] fcmp7_rd computed checksum for lane 7 (see description for register 0x40e) . 0 x 0 r 0 x 450 ils _did [7:0] did did is the device id number. 0 x 0 r/w link information received on lane 0 as specified in section 8.3 of jesd 204b. must be set to value read in register 0x400 . 0 x 451 ils_bid [7:4] adjcnt adjcnt is the adj ustment resolutio n to dac lmfc. 0 x 0 r/w link information received on lane 0 as specified in section 8.3 of jesd 204b. [3:0] bid bid is the bank id extension to did . 0 x 0 r/w link information received on lane 0 as specified in section 8.3 of jesd 204b. must be set to value read in register 0x401[3:0] . 0 x 452 ils_lid0 7 reserved reserved. 0 x 0 r 6 adjdir adjdir is the direction to adjust dac lmfc . 0 x 0 r/w link information received on lane 0 as specified in section 8.3 of jesd 204b. 5 phadj phadj is the phase adjustment request t o dac . 0 x 0 r/w link information received on lane 0 as specified in section 8.3 of jesd 204b. [4:0] lid0 lid0 is the lane identification for lane 0 . 0 x 0 r/w link information received o n lane 0 as specified in section 8.3 of jesd 204b.
data sheet AD9154 rev. b | page 117 of 124 addr. name bits bit name settings description reset access 0 x 453 ils_scr_l 7 scr scr is the rx de scrambling enable . 0 x 1 r/w 0 is disabled . 1 is enabled . [6:5] reserved reserved. 0 x 0 r [4:0] l l is the number of lanes per converter device 0 x 3 r/w settings of 2, 4 , and 8 are valid for single single link mode. settings of 1, 2 , and 4 are valid for dual link mode. 00000 1 lane . 00001 2 lanes . 00011 4 lanes . 00111 8 lanes . 0 x 454 ils_f [7:0] f this value of f is not used to soft configure the qbd. the re gister ctrlreg1 is used to soft configure the qbd. 0 x 0 r/w 0 x 455 ils_k [7:5] reserved reserved. 0 x 0 r [4:0] k k is the number of frames per multiframe . 0 x 1 f r/w settings of 1 6 or 32 are valid. must be set to 32 when f = 4 (register 0x476) . 01111 = 16 . 11111 = 32 . 0 x 456 ils_m [7:0] m m is the number of converters/device . 0 x 1 r settings of 1, 2, and 4 are valid for single link mode. settings of 1 and 2 are valid in dual link mode. refer to table 15 and table 16. 0 1 converter per device . 1 2 converters per device . 3 4 converters per dev ice . 0 x 457 ils_cs_n [7:6] cs cs is the number of control bits/sample . 0 x 0 r/w must be set to 0 . control bits are not supported. 5 reserved reserved. 0 x 0 r [4:0] n n = converter resolution . 0 x 1 f r/w must be set to 16 (0x0f ) . 0 x 458 ils_np [7:5] subclassv subclassv = device subclass version . 0 x 1 r/w must be set to 1 (3'b001) . [4:0] np np = total no. of bits/sample . 0 xf r/w must be set to 16 (0x0f). refer to ta ble 15 and table 16. 0 x 459 ils_s [7:5] jesdv er jesdv is the jesd204 version . 0 x 1 r/w 0 jesd204a . 1 jesd204b . [4:0] s s = no. of samples/converter per frame cycle . 0 x 0 r/w settings of 1 and 2 are valid. refer to table 15 and table 16. s = 00000 - > 1 sample . s = 00001 - > 2 samples. 0 x 45 a ils_hd_cf 7 hd hd is high dens ity mode . 0 x 1 r/w refer to section 5.1.3 of jesd204b standard . 0 density mode . 1 density mode . [6:5] reserved reserved. 0 x 0 r [4:0] cf cf is the number of control words per frame clock period per link . 0 x 0 r/w must be set to 0 . control bits are not supported.
AD9154 data sheet rev. b | page 118 of 124 addr. name bits bit name settings description reset access 0 x 45d ils_checksum [7:0] lane0 - checksum checksum for lane 0 . 0 x 45 r/w the checksum for the values programmed into register 0x450 to register 0x45c must be calculated according to section 8 .3 of the j esd204b spec and written here [ sum( register 0x450 C register 0x45c) % 256 ] . 0 x 46b errcntrmon 7 reserved reserved. 0 x 0 r [6:4] lanesel lane select for jesd 204b error counter . 0 x 0 w writing these bits selects the jesd lane to mo nitor the error type designated by the register write to cntrsel ( bits 1:0] ) baddiscntr , nitcntr and uekccntr error counters in each lane are accessed via indirect addressing. to read a counter value, the lanesel and cntrsel are first written , then the rea d back accesses the desired counter. 0 selects lane 0 . 1 selects lane 1 . 3 selects lane 2 . 3 selects lane 3 . 4 selects lane 4 . 5 selects lane 5 . 6 selects lane 6 . 7 selects lane 7 . [3:2] reserved reserved. 0 x 0 r [7:0] readerrorcntr read jesd 204b error counter . 0 x 0 r after selecting the lane and error counter by writing to lanesel ( bits[ 6:4 ] ) and cntrsel (1:0), the selected error counter is re ad back here. [1:0] cntrsel jesd 204b error counter select . 0 x 0 w w riting these bits allows the readback of the following jesd 204b errors for the lane designated by the register write to lanesel ( bits[ 6:4 ] ). to read a counter value, the lanesel and cntrsel are first written, then the read back access the desired counter . 0 baddiscntr: bad running disparity counter . 1 nitcntr: not in table error counter . 2 ucccntr: unexpected control character counter . 0x46 c lanedeskew [7:0] lanedeskew lane de skew . 0 xf r/w enabled on a per lane basis by writing 1 to the appropriate bit position : bit s[ 7:0 ] map to lane 7 to lane 0. note th at in dual link mode, only bits[ 3:0 ] are used for each link . 1 : deskew en abled for lane 0 . 1 : deskew enabled for lane 1 . 1: deskew enabled for lane 2 . 1: deskew enabled for lane 3 . 1: deskew enabled for lane 4 . 1: deskew enabled for lane 5 . 1: deskew enabled for lane 6 . 1: deskew enabled for lane 7 .
data sheet AD9154 rev. b | page 119 of 124 addr. name bits bit name settings description reset access 0 x 46d baddisparity 7 rstirq _dis reset baddis irq counter for lane selected via bits[ 2:0 ] by writing 1 to this bit . 0 x 0 w 6 disable_errcnt _dis disable the baddis error counter for lane sele cted via bits[ 2:0 ] by writing 1 to this bit . 0 x 0 w 5 rsterrcntr _dis reset baddis error counter for lane sele cted via bits[ 2:0 ] by writing 1 to this bit . 0 x 0 w [4:3] reserved reserved. 0 x 0 r [7:0] baddis bad disparity character error (baddis) . 0 x 0 r each bit corr esponds to each lane. the error count can be accessed via register 0x46b. note that in dual link mode, only bits[ 3:0 ] are used for each link. 1 baddisparitycharacter error c ount has reached the threshold count of register 0x7c for any lane with its corresponding bit set when reading this register . 0 bad disparity character error count has not reached the threshold count . [2:0] laneaddr _dis lane address for functions described in bits[ 7:5 ] 0 x 0 w 0 x 46e nitdisparity 7 rstirq _ni t reset irq for lane selected via bits[ 2:0 ] by writing 1 to this bit . 0 x 0 w 6 disable_ errcnt _nit disable the error cou nter for lane selected via bits[ 2:0 ] by writing 1 to this bit . 0 x 0 w 5 rsterrcntr _nit reset error counter for lane selected v ia bits[ 2:0 ] by writing 1 to this bit . 0 x 0 w [ 4:3 ] reserved reserved. 0 x 0 r [7:0] nitd not in table disparity character error (nitd) . 0 x 0 r each bit corresponds to each lane. the error count can be accessed via register 0x46b . note th at i n dual link mode, only bits[ 3:0 ] are used for each link . [2:0] laneaddr _nit lane address for functions described in bits[ 7:5 ]. 0 x 0 w 0 x 46f unexpectedk char 7 rstirq _k reset irq for lane se lected via bits[2:0] by writing 1 to this bit . 0 x 0 w 6 disable_errcnt _k disable the error cou nter for lane selected via bits[ 2:0 ] by writing 1 to this bit . 0 x 0 w 5 rsterrcntr _k reset error cou nter for lane selected via bits[ 2:0 ] by writing 1 to this bit . 0 x 0 w [ 4:3 ] reserved reserved. 0 x 0 r [ 2:0] laneaddr _k lane address for functions described in bits[ 7:5 ]. 0 x 0 w 0 x 470 codegrp - syncflg [7:0] codegrpsync code group sync flag (from each instantiated lane) 0 x 0 r/w writing 1 to bit 7 resets the irq. the associated irq flag is located in register 0 x 470[ 0 ]. a loss of codegrpsync triggers sync request assertion. refer to the sysref, syncout, and the deterministic latency section . 1 on bit x of this register = synchronization was achie ved on lane l . 0 on bit x of this register = sy nchronization was lost on lane x. 0 x 471 framesync - flg [7:0] framesync frame sync flag (from each instantiated lane) . 0 x 0 r/w this register indicates the live status for each lane. wr iting 1 to bit 7 resets the irq. a loss of frame sync automatically initiates a synchronization sequence. 0 x 472 goodchk - sumflg [7:0] good - checksum good check sum flag (from each instantiated lane . ) 0 x 0 r/w writing 1 to bit 7 resets the irq. the associated irq flag is located in register 0 x 470[ 2 ].
AD9154 data sheet rev. b | page 120 of 124 addr. name bits bit name settings description reset access 0 x 473 initlane - syncflg [7:0] initiallanesync initial lane sync flag (from each instantiated lane) . 0 x 0 r/w writing 1 to bit 7 resets the irq. the associated irq flag is located in reg ister 0 x 470[ 2 ]. loss of synchronization is also reported on syncout . refer to the sysref, syncout , and the deterministic latency section . 0 x 476 ctrlreg1 [7:0] f_again f is the number of octets per frame . 0 x 1 r/w settings of 1, 2, and 4 are valid. refer to table 15 and table 16. 0 x 477 ctrlreg2 7 ilas_mode ilas test mode . 0x0 r/w defined in section 5.3.3.8 of jesd204b spec ification. 1 jesd204b receiver is constantly receiving ilas frames . 0 normal link operation . [ 6 :4] reserved reserved. 0 x 0 r 3 threshold_ mask_en threshold mask en able. set this bit if using sync_assertion_mask (register 0x47b[7:5]). 0 x 0 r/w [2:0] reserved reserved. 0 x 0 r 0 x 478 kval [7:0] ksync number of 4 k multiframes during ilas . 0 x 1 r/w sets the number of multiframes to send lane alignment sequ ence during the initial lane alignment. 1 = 4 k multiframes . 0x47a irqvector 7 baddis_flag bad disparity error count. 0 x 0 r 1 bad disparity character count reached errorthresh ( register 0x47c) on at least one lane. read register 0x46d t o determine which lanes are in error. 7 baddis_mask bad disparity mask. 0 x 0 w 1 if the bad disparity count reaches errorthresh on any lane, irq is pulled low. 6 nitd_mask not in table mask. 0 x 0 w 1 if t he not in table character count reaches errorthresh on any lane, irq is pulled low. 6 nitd_flag not in table error count . 0 x 0 r 1 not in table character count reached errorthresh ( register 0x47c) on at least one lane. r ead register 0 x 46 e to determine which lanes are in error. 5 uekc_flag unexpected control character error count . 0 x 0 r 1 unexpected control character count reached errorthresh (0x47c) on at least one lane. read register 0x46f to determine which lanes are in error. 5 uekc_mask unexpected control character mask. 0 x 0 w 1 if the unexpected control character count reaches errorthresh on any lane, irq is pulled low. 4 reserved reserved. 0 x 0 r 3 initiallanesync _flag unexpected control character error count . 0 x 0 r 1 unexpected control character count reached errorthresh ( register 0 x 47 c) on at least one lane. read register 0 x 46 f to determine which lanes are in error. 3 initiallan esync _mask initial lane sync mask. 0 x 0 w 1 if initial lane sync ( register 0x473) fails on any lane, irq is pulled low.
data sheet AD9154 rev. b | page 121 of 124 addr. name bits bit name settings description reset access 2 badchecksum_ mask bad checksum mask. 0 x 0 w 1 if there is a bad checksum ( register 0x472) on any lane, irq is pulled low. 2 badchecksum_ flag bad checksum flag. 0 x 0 r 1 bad checksum on at least one lane. read register 0x472 to determine which lanes are in error. 1 reserved reserved. 0 x 0 r 0 c odegrpsync_ flag 1 code group sync flag. code group sync failed on at least one lane. read register 0x470 to determine which lanes are in error . 0 x 0 r code group sync failed on at least one lane. read register 0x470 to determine which lanes are i n error . 0 codegrpsync_ mask 1 code group sync machine mask. if code group sync ( register 0x470) fails on any lane, irq is pulled low. 0 x 0 w 0 x 47b syncassert - ion mask 7 baddis_s bad disparity error on sync. 0 x 0 r/w 1 as serts a sync request on syncoutx when the bad disparity character count reaches the threshold in register 0x47c . 6 nit_s not in table error on sync. 0 x 0 r/w 1 asserts a sync request on syncoutx when the not in table character count reaches the threshold in register 0x47c . 5 ucc_s unexpected control character error on sync. 0 x 0 r/w 1 asserts a sync request on syncoutx when the unexpected control character count rea ches the threshold in register 0x47c . 4 cmm configuration mismatch irq. if cmm_enable is high, this bit latches on a rising edge and pull irq low. when latched, write a 1 to clear this bit. if cmm_enable is low, this bit is non - functional. 0 x 0 r /w 1 link lane 0 configuration registers (register 0x450 to register 0x45d) do not match the jesd204b transmit settings (register 0x400 to register 0x40d) . configuration mismatch irq. if cmm_enable is high, this bit latch es on a rising edge and pull irq low. when latched, write a 1 to clear this bit. if cmm_enable is low, this bit is non - functional. 3 cmm_enable configuration mismatch irq enable. 0 x 1 r/w 1 enables irq generation if a c onfiguration mismatch is detected . 0 configuration mismatch irq disabled . mismatch irq disabled . [2:0] reserved reserved. 0 x 0 r 0 x 47 c errorthres [7:0] eth error threshold. bad disparity, not in table, and unexpected contro l character errors are counted and compared to the error threshold value. when the count reaches the threshold, either an irq is generated or the syncoutx signal is asserted per the mask register settings, or both. function is performed in all lanes. 0 xff r/w 0 x 47d laneenable [7:0] lane_ena lane enable. setting bit x enables link lane x. 0 xf r/w this register must be programmed before receiving the code group pattern for proper operation. 0 x 47e ramp_ena [7:1] reserved reser ved. 0 x 0 r
AD9154 data sheet rev. b | page 122 of 124 addr. name bits bit name settings description reset access 0 ena_ramp_ check enable ramp checking at the beginning of ilas. 0 x 0 r/w 0 disable ramp checking at beginning of ilas; ilas data need not be a ramp . 1 enable ramp checking; ilas data needs to be a ramp starting at 00 -01 - 02; otherwise, the r amp ilas fails and the device does not start up . 0 x 520 dig_test0 [7: 2 ] reserved reserved. 0 x 0 r 1 dc_test_mod dc test mode enable . 0 x 0 r/w 0 reserved reserved . 0 x 0 r/w 0 x 521 test_dc_ valuei 0 [ 7:0 ] test_dc_ valu ei0 dc value lsb of f s /8 and decoder testing for i dac . 0 x 0 r/w 0 x 522 test_dc_ valuei 1 [ 7:0 ] test_dc_ valuei 1 dc value msb of f s /8 and decoder testing for i dac . 0 x 0 r/w 0 x 523 test_dc_ valueq 0 [ 7:0 ] test_dc_ valueq 0 dc value lsb of f s /8 and decod er testing for q dac . 0 x 0 r/w 0 x 524 test_dc_ valueq 1 [ 7:0 ] test_dc_ valueq 1 dc value msb of f s /8 and decoder testing for q dac . 0 x 0 r/w
data sheet AD9154 rev . b | page 123 of 124 outline dimensions figure 89 . 88 - lead lead frame chip scale package [lfcsp_vq] 12 m m 12 mm body, very thin quad (cp - 88 - 6) dimensions shown in millimeters figure 90 . 88 - lead lead frame chip scale package [lfcsp_vq] 12 mm 12 mm body, very thin quad (cp - 88 - 9) dimensions shown in millimeters compliant t o jedec s t andards mo-220-vrrd 1 22 66 45 23 44 88 67 0.50 0.40 0.30 0.28 0.23 0.18 10.50 ref 0.60 max 0.60 max 7.55 7.40 sq 7.25 0.50 bsc 0.20 ref 12 max sea ting plane pin 1 indic a t or 0.70 0.65 0.60 0.045 0.025 0.005 pin 1 indic a t or t o p view 0.90 0.85 0.80 exposed pad bottom view for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarit y 0.08 12.10 12.00 sq 1 1.90 1 1.85 1 1.75 sq 1 1.65 08-10-2012- a compliant t o jedec s t andards mo-220 1 22 66 45 23 44 88 67 0.50 0.40 0.30 0.80 0.70 0.60 1.00 0.90 0.80 0.65 0.55 0.45 0.30 0.25 0.20 10.50 ref 0.60 max 0.60 max 7.55 7.40 sq 5.25 0.50 bsc 0.190~0.245 ref 12 max se a ting plane pin 1 indic a t or 0.70 0.65 0.60 0.045 0.025 0.005 pin 1 indic a t or t o p view 0.90 0.85 0.80 exposed pad bot t om view for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarit y 0.08 12.10 12.00 sq 1 1.90 1 1.85 1 1.75 sq 1 1.65 08-04-2014- a pkg-004598
AD9154 data sheet rev. b | page 124 of 124 ordering guide model 1 temperature range package description package option ad 9154 bcpz ? 40 c to + 85 c 88 - lead lfcsp _vq cp -88 -6 ad 9154 bcpzrl ? 40 c to + 85 c 88 - lead lfcsp _vq cp -88 -6 AD9154bcp a z ? 40 c to + 85 c 88 - lead lfcsp _vq (variable lead length) cp -88 -9 AD9154bcp a zrl ? 40 c to + 85 c 88 - lead lfcsp _vq (variable lead length) cp -88 -9 ad9 154 - ebz dpg3 evaluation board AD9154 - fmc- ebz fmc evaluation board AD9154 - m6720 - ebz dpg3 evaluation board with adrf6720 - 27 modulator 1 z = rohs compliant part. ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11389 - 0- 7/15(b)

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